P8044AH-R0117 datasheet(3/65 Pages) INNOVASIC

3 / 65 page

IA8044/IA8344

Data Sheet

SDLC Communications Controller

March 30, 2010

IA211010112-04

http://www.Innovasic.com

UNCONTROLLED WHEN PRINTED OR COPIED

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Page 3 of 65

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TABLE OF CONTENTS

List of Figures ..................................................................................................................................6

List of Tables ...................................................................................................................................7

Introduction.............................................................................................................................9

1.1

Features .........................................................................................................................9

1.2

Variants .......................................................................................................................10

Packaging, Pin Descriptions, and Physical Dimensions.......................................................10

2.1

PDIP Package ..............................................................................................................11

2.2

PDIP Physical Dimensions..........................................................................................13

2.3

PLCC Package.............................................................................................................14

2.4

PLCC Physical Dimensions ........................................................................................16

Maximum Ratings and DC Characteristics ..........................................................................17

Functional Description..........................................................................................................17

4.1

Functional Block Diagram ..........................................................................................17

4.2

Input/Output Characteristics .......................................................................................19

4.3

Memory Organization .................................................................................................20

4.3.1

Program Memory............................................................................................20

4.3.2

External Data Memory ...................................................................................20

4.3.3

Internal Data Memory.....................................................................................20

4.3.4

Bit Addressable Memory................................................................................22

4.4

Special Function Registers ..........................................................................................23

4.5

Ports.............................................................................................................................24

4.6

Port Registers ..............................................................................................................24

4.6.1

Port 0 (P0).......................................................................................................24

4.6.2

Port 1 (P1).......................................................................................................25

4.6.3

Port 2 (P2).......................................................................................................25

4.6.4

Port 3 (P3).......................................................................................................25

4.7

Timers/Counters ..........................................................................................................26

4.7.1

Timers 0 and 1 ................................................................................................26

4.7.2

Mode 0 ............................................................................................................26

4.7.3

Mode 1 ............................................................................................................27

4.7.4

Mode 2 ............................................................................................................27

4.7.5

Mode 3 ............................................................................................................27

4.7.6

Timer Mode (TMOD).....................................................................................27

4.7.7

Timer Control (TCON)...................................................................................28

4.7.8

Timer 0 High Byte (TH0) ...............................................................................29

4.7.9

Timer 0 Low Byte (TL0) ................................................................................29

4.7.10 Timer 1 High Byte (TH1) ...............................................................................29

4.7.11 Timer 1 Low Byte (TL1) ................................................................................29

4.7.12 Timer/Counter Configuration .........................................................................30

4.8

General CPU Registers................................................................................................32

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