AM79C90PC datasheet(20/62 Pages) AMD

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AMD

P R E L I M I N A R Y

Am79C90

RES

CSR 1:0

17881B-14

Bit

Name

Description

15:02

RES

Reserved. Read as zeroes. Write as

zeroes.

01:00

CSR(1:0)

CSR address select. READ/WRITE.

Selects the CSR to be accessed

through the RDP. RAP is cleared by

Bus

RESET.

CSR(1 :0)

CSR

Control and Status Register Definition

Control and Status Register 0 (CSR0)

ERR

BABL

CERR

MISS

MERR

RINT

TINT

IDON

INIT

STRT

STOP

TDMD

TXON

RXON

INEA

INTR

The C-LANCE updates CSR0 by logical “ORing” the pre-

vious and present value of CSR0.

17881B-15

Bit

Name

Description

ERR

ERROR summary is set by the

“ORing” of BABL, CERR, MISS and

MERR. ERR remains set as long as

any of the error flags are true.

ERR is read only; writing it has no ef-

fect. It is cleared by Bus

RESET, set-

ting the STOP bit, or clearing the

individual error flags.

Bit

Name

Description

BABL

BABBLE is a transmitter timeout er-

ror. It indicates that the transmitter

has been on the channel longer than

the time required to send the maxi-

mum length packet.

BABL is a flag which indicates ex-

cessive length in the transmit buffer.

It will be set after 1519 bytes have

been transmitted, excluding pream-

ble and start frame delimiter; the

C-LANCE will continue to transmit

until the whole packet is transmitted

or until there is a failure before the

whole packet is transmitted. When

BABL error occurs, an interrupt will

be generated if INEA = 1.

BABL is READ/CLEAR ONLY and is

set by the C-LANCE, and cleared by

writing a “1” into the bit. Writing a ”0”

has no effect. It is cleared by

RESET

or by setting the STOP bit.

CERR

COLLISION ERROR indicates that

the collision input to the C-LANCE

was not asserted during the trans-

mission, nor within 4.0

µs after the

transmit completed. The collision af-

ter transmission is a transceiver test

feature. This function is also known

as heartbeat or SQE (Signal Quality

Error) test.

CERR is READ/CLEAR ONLY and

is set by the C-LANCE and cleared

by writing a “1” into the bit. Writing a

“0” has no effect. It is cleared by

RE-

SET or by setting the STOP bit.

CERR error will not cause an inter-

rupt to occur (INTR = 0).

MISS

MISSED PACKET is set when the

receiver loses a packet because it

does not own any receive buffer, in-

dicating loss of data.

FIFO overflow is not reported be-

cause there is no receive ring entry

in which to write status.

When MISS is set, an interrupt will

be generated if INEA = 1.

MISS is READ/CLEAR ONLY, and is

set by the C-LANCE and cleared by

writing a “1” into the bit. Writing a “0”

has no effect. It is cleared by

RESET

or by setting the STOP bit.

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