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AM79C90PC 数据表(PDF) 43 Page - Advanced Micro Devices |
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AM79C90PC 数据表(HTML) 43 Page - Advanced Micro Devices |
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43 / 62 page ![]() P R E L I M I N A R Y AMD 43 Am79C90 SWITCHING WAVEFORMS TCLK TX TENA RENA 4 5 17881B-41 *During transmit, RENA input must be asserted (HIGH) and remain active-HIGH before TENA goes inactive (LOW). If RENA is deasserted before TENA is deasserted, LCAR will be reported in TMD3 after the transmission is completed by the C-LANCE. 8 9 2 3 1 7 * 6 Serial Link Timing (Transmit) Drivers Enabled O.D. 23 22 24 21 HOLD HLDA Bus Master Drivers RESET Note: 1. RESET is an asynchronous input to the C-LANCE and is not part of the Bus Acquisition timing. When RESET is asserted, the C-LANCE becomes a Bus Slave. 17881B-42 Bus Acquisition Timing |
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