AM79C90PC datasheet(13/62 Pages) AMD

13 / 62 page

P R E L I M I N A R Y

AMD

Am79C90

the BYTE scheme is chosen, the

BM1 pin can be used

for performing the function

BUSAKO.

BCON is also used to program pins for different DMA

modes. In a daisy chain DMA scheme, 3 signals are

used (

BUSRQ, HLDA, BUSAKO). In systems using a

DMA controller for arbitration, only

HOLD and HLDA are

used.

C-LANCE in Bus Slave Mode

The C-LANCE enters the Bus Slave Mode whenever

becomes active. This mode must be entered whenever

writing or reading the four status control registers

(CSR0, CSR1, CSR2, and CSR3) and the Register Ad-

dress Pointer (RAP). RAP and CSR0 may be read or

written to at anytime, but the C-LANCE must be stopped

(by setting the stop bit in CSR0) for CSR1, CSR2, and

CSR3 access.

Read Sequence (Slave Mode)

At the beginning of a read cycle,

CS, READ, and DAS

are asserted. ADR must be valid at this time. (If ADR is a

“1,” the contents of RAP are placed on the DAL lines.

Otherwise the contents of the CSR register addressed

by RAP are placed on the DAL lines.) After the data on

the DAL lines become valid, the C-LANCE asserts

READY, CS, READ, DAS, and ADR must remain stable

throughout the cycle. Refer to Figure 3.

Write Sequence (Slave Mode)

This cycle is similar to the read cycle, except that during

this cycle, READ is not asserted (READ is LOW). The

DAL buffers are tristated which configures these lines as

inputs. The assertion of

READY by C-LANCE indicates

to the memory device that the data on the DAL lines

have been stored by C-LANCE in its appropriate CSR

CS, READ, DAS, ADR and DAL 15:00 must re-

main stable throughout the write cycle. Refer to

Figure 4.

Note: Setting the STOP bit in the C-LANCE will gener-

ate a C-LANCE reset, which will cause all bus control

output signals (including

READY) to float. To guarantee

slave write timing when the STOP bit is being set in

CSR0, the C-LANCE will latch the STOP bit and will wait

for the slave cycle to complete before resetting itself and

floating the output signals.

C-LANCE in Bus Master Mode

All data transfers from the C-LANCE in the bus Master

mode are timed by ALE,

DAS, and READY. The auto-

matic adjustment of the C-LANCE cycle by the

READY

signal allows synchronization with variable cycle time

memory due either to memory refresh or to dual port ac-

cess. Transfers are a minimum of 600 ns in length ex-

cept for the first transfer of a bus mastership period in

which the minimum is 700 ns. Transfers can be in-

creased in 100 ns increments.

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