AM79C90PC datasheet(33/62 Pages) AMD

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P R E L I M I N A R Y

AMD

Am79C90

BSWP=0:

FIFO BYTE n

gets DAL <07:00>

–don’t care

gets DAL <15:08>

BSWP=1:

FIFO BYTE n

gets DAL <15:08>

–don’t care

gets DAL <07:00>

TRANSMISSION – BYTE READ FROM ODD

MEMORY ADDRESS

BSWP=0:

FIFO BYTE n

gets DAL <15:08>

–don’t care

gets DAL <07:00>

BSWP=1:

FIFO BYTE n

gets DAL <07:00>

–don’t care

gets DAL <15:08>

RECEPTION – WORD WRITE TO EVEN MEMORY

ADDRESS

BSWP=0:

DAL <07:00>

gets FIFO BYTE n

DAL <15:08>

gets FIFO BYTE n + 1

BSWP=1:

DAL <15:08>

gets FIFO BYTE n

DAL <07:00>

gets FIFO BYTE n + 1

RECEPTION – BYTE WRITE TO EVEN MEMORY

ADDRESS

BSWP=0:

DAL <07:00>

gets FIFO BYTE n

DAL <15:08>

–undefined

BSWP=1:

DAL <15:08>

gets FIFO BYTE n

DAL <07:00>

–undefined

RECEPTION – BYTE WRITE TO ODD MEMORY

ADDRESS

BSWP=0:

DAL <07:00>

–undefined

DAL <15:08>

gets FIFO BYTE n

BSWP=1:

DAL <15:08>

–undefined

DAL <07:00>

gets FIFO BYTE n

The C-LANCE Recovery and

Reinitialization

The transmitter and receiver section of the C-LANCE

are turned on via the initialization block (MODE REG:

DRX, DTX bits). The state of the transmitter and the re-

ceiver are monitored through the CSR0 register (RXON,

TXON bits). The C-LANCE must be reinitialized if the

transmitter and/or the receiver has not been turned on

during the original initialization, and later it is desired to

have them turned on. When either the transmitter or re-

ceiver shuts off because an error (MERR, UFLO, TX

BUFF error), it is necessary to reinitialize the C-LANCE

to turn the transmitter and/or receiver back on again.

The user should rearrange the descriptors in the trans-

mit or receive ring prior to reinitialization. This is neces-

sary since the transmit and receive descriptor pointers

are reset to the beginning of the ring upon initialization.

To reinitialize the C-LANCE, the user must first stop the

C-LANCE by setting the stop bit in CSR0. The user

needs to reprogram CSR3 because its contents get

cleared when the stop bit gets set (CSR3 reprogram-

ming is not needed when default values of BCON,

ACON, and BSWP are used; BCON, ACON, and BSWP

default values are 0, 0, and 0 respectively). Only then

the user may set the INIT bit in CSR0.

It is recommended that the C-LANCE not be re-started,

once it has been stopped (STOP = 1 in CSR0), by set-

ting the STRT bit in CSR0 without reinitialization. Re-

starting the C-LANCE in this way puts the C-LANCE in

operation in accordance with the parameters set up in

the mode register, but the contents of the descriptor

pointers in the C-LANCE will not be guaranteed.

Frame Formatting

The C-LANCE performs the encapsulation/decapsula-

tion function of the data link layer (second layer of ISO

model) as follows:

Transmlt

In transmit mode, the user must supply the destination

address, source address, and Type Field (or Length

Field) as a part of data in transmit data buffer memory.

The C-LANCE will append the preamble, SFD, and

CRC (FCS) to the frame as is shown in Figures 9-1

and 9-2.

Receive

In receive mode, the C-LANCE strips off the preamble

and SFD and transfers the rest of the frame, including

the CRC bytes (4 bytes), to the memory. The C-LANCE

will discard packets with less than 64 bytes (runt packet)

and will reuse the receive buffer for the next packet. This

is the only case where the packet is discarded after the

packet has been transferred to the receive buffer. A runt

packet is normally the result of a collision.

Preamble

1010 ... 1010

Synch

Dest.

ADR

Source

ADR

Type

Data

FCS

Bits

Bytes

46–1500

Bytes

17881B-35

Figure 9-1. Ethernet Frame Format

LLC

Data

Preamble

1010 ... 1010

SFD

10101011

Dest.

ADR

Source

ADR

Length

FCS

Bits

Bytes

46–1500

Bytes

17881B-36

PAD

Figure 9-2. IEEE 802.3 MAC Frame Format

Framing Error (Dribbling Bits)

The C-LANCE can handle up to 7 dribbling bits when a

received packet terminates; the input to the C-LANCE,

RCLK, stops following the deassertion of RENA. During

the reception, the CRC is generated on every serial bit

(including the dribbling bits) coming from the medium,

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