AM79C90PC datasheet(32/62 Pages) AMD

32 / 62 page

AMD

P R E L I M I N A R Y

Am79C90

17881B-33

127

Output

Packet

Figure 8-1. Data Chaining (Transmit)

Notes:

1. W, X, Y, Z are the packets queued for transmission.

2. A, B, C, D are the packets received by the C-LANCE.

17881B-34

127

C-LANCE

CPU

(Note

C-LANCE

127

(Note

CPU

Transmit

Receive

Figure 8-2. Buffer Management Descriptor Rings

C-LANCE DMA Transfer

(Bus Master Mode)

There are two types of DMA Transfers with the

C-LANCE:

Burst mode DMA

Single word DMA

Burst Mode DMA

Burst DMA is used for Transmission or Reception of the

Packets, (Read/Write from/to Memory).

The Burst Transfers are 8 consecutive word reads

(transmit) or writes (receive) that are done in a single

bus arbitration cycle. In other words, once the C-LANCE

receives the bus acknowledge, (

HLDA = LOW), it will do

8 word transfers (8 DMA cycle, min. at 600 ns per cycle)

without releasing the bus request signal (

HOLD =

LOW). If there are more than 16 bytes empty in the

Transmit FIFO, in transmit mode, or at least 16 bytes of

data, in the Receive FIFO in receive mode, when the

C-LANCE releases the bus (

HOLD deasserted), the

C-LANCE will request the bus again within 700 ns

(

HOLD dwell time). Burst DMAs are always 8 transfer

cycles unless there are fewer than 8 words left to be

transferred to/from the Transmit/Receive FIFO, or if

there are fewer than 8 words left to be transferred to/

from the RX/TX buffer. Transmit DMAs may be shorter

than 8 words if a collision is detected during the DMA.

Single Word DMA Transfer

The C-LANCE initiates single word DMA transfers to ac-

cess the transmit and receive rings or the initialization

block. The C-LANCE will not initiate any burst DMA

transfers while reading the initialization block.

The

C-LANCE will not initiate any burst DMA transfers be-

tween the time that it discovers ownership of a descrip-

tor and the time that it reads the buffer pointer and buffer

byte count entries of that descriptor.

FIFO Operation

The dual FIFOs provide temporary buffer storage for

data being transferred between the parallel bus l/O pins

and serial I/O pins. The capacity of the Transmit FIFO is

48 bytes and the Receive FIFO is 64 bytes.

Transmit

Data is loaded into the Transmit FIFO under internal

microprogram control. The Transmit FIFO has to have

more than 16 bytes empty before the C-LANCE re-

quests the bus (

HOLD is asserted). The C-LANCE will

start sending the preamble (if the line is idle) as soon as

the first byte is loaded to the Transmit FIFO from

memory.

Receive

Data is loaded into the Receive FIFO from the serial in-

put shift register during reception. Data leaves the Re-

ceive FIFO under microprogram control. The C-LANCE

microcode will wait until there are at least 16 bytes of

data in the Receive FIFO before initiating a DMA burst

transfer. Preamble and Start Frame Delimiter (SFD) are

not loaded into the Receive FIFO.

FIFOs – Memory Byte Alignment

Memory buffers may begin and end on arbitrary byte

boundaries. Parallel data is byte aligned between the

Transmit

Receive

FIFO

and

DAL

lines

(DAL0–DAL15). Byte alignment can be reversed by set-

ting the Byte Swap (BSWP) bit in CSR3.

TRANSMISSION – WORD READ FROM EVEN MEM-

ORY ADDRESS

BSWP=0:

FIFO BYTE n

gets DAL <07:00>

FIFO BYTE n + 1 gets DAL <15:08>

BSWP=1:

FIFO BYTE n

gets DAL <15:08>

FIFO BYTE n + 1 gets DAL <07:00>

TRANSMISSION – BYTE READ FROM EVEN

MEMORY ADDRESS

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