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AM79C90PC 数据表(PDF) 40 Page - Advanced Micro Devices |
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AM79C90PC 数据表(HTML) 40 Page - Advanced Micro Devices |
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40 / 62 page ![]() AMD P R E L I M I N A R Y 40 Am79C90 SWITCHING CHARACTERISTICS (continued) Parameter Test No. Symbol Parameter Description Conditions Min Typ Max Unit 55 tSAH ADR Hold Time After the Rising Edge of DAS (Bus Slave) 0 ns 56 tSAS ADR Setup Time to the Falling Edge of DAS (Bus Slave) 0 ns 57 tARYD Delay from the Falling Edge of ALE to the 80 ns Falling Edge of READY to insure a Minimum Bus Cycle Time (600 ns) (Note 5) 58 tSRDS Data Setup Time to the Falling Edge of READY (Bus Slave Read) 75 ns 59 tRDYH READY Hold Time After the Rising Edge of DAS (Bus Master) 0 ns 60 tSR01 READY Driver Turn On After the Falling (CSR0, CSR3, RAP) 6tTCT ns Edge of DAS (Bus Slave) (Notes 4, 6) 61 tSR02 READY Driver Turn On After the Falling (CSR1, 2) 14tTCT ns Edge of DAS (Bus Slave) (Note 6) 62 tSRYH READY Hold Time After the Rising Edge of DAS (Bus Slave) 0 35 ns 63 tSRH READ Hold Time After the Rising Edge of DAS (Bus Slave) 0 ns 64 tSRS READ Setup Time to the Falling Edge of DAS (Bus Slave) 0 ns 65 tCHL TCLK Rising Edge to HOLD LOW or High 95 ns Delay 66 tCAV TCLK to Address Valid 100 ns 67 tCCA TCLK Rising Edge to Control Signals Active 75 ns 68 tCALE TCLK Falling Edge to ALE LOW 90 ns 69 tCDL TCLK Falling Edge to DAS Falling Edge 90 ns 70 tRCS Ready Setup Time to TCLK Falling Edge (Note 5) 0 ns 71 tCDH TCLK Rising Edge to DAS HIGH 90 ns 72 tHCS HLDA Setup to TCLK Falling Edge 0 ns 73 tRENH RENA Hold Time After the Rising Edge of 0 ns RCLK 74 tCSR CS recovery time between deassertion tTCT+60 ns of CS or HOLD and assertion of CS Notes: 1. Not shown in the timing diagrams, specifies the minimum bus cycle for a single DMA data transfer. Tested by functional data pattern. 2. Applicable parameters associated with Receive circuit are tested at tRCT (RCLK Period) = 100 ns, tTCT = 100 ns (TCLK Period). 3. Not tested. 4. CSR0 write access time (tSR01) when STOP bit is being set can be as long as 12tTCT. 5. It is guaranteed that no wait states will be added by the C-LANCE if either parameter #57 or #70 is met. 6. Parameter is for design reference only. 7. Reset must be asserted for at least two rising and two falling edges of TCLK for the device to be reset. If reset is deasserted before TCLK starts, the device behavior is undefined. |
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