AM79C90PC datasheet(56/62 Pages) AMD

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Am79C90

Table B-1.

Comparison Summary of the C-LANCE and LANCE Devices

Description

Am79C90 C-LANCE

Am7990 LANCE

Process/Power

Consumption

0.8-micron CS-21S CMOS process

CC ≤ 50 mA

NS-8B NMOS process

CC ≤ 270 mA

FIFOs

Dual FIFOs: 48-byte TX, 64-byte RX

Single FIFO: 48-byte TX/RX

Transmit Lockout Due to

Receive

Will not occur with dual FIFOs and

enhanced microcode.

May occur in high receive rate situations

with “less than optimal” bus latencies.

Per-Packet FCS

Transmit descriptor bit is used to allow per-

packet addition of CRC when DTCR is set in

the MODE register.

No per-packet CRC control provided.

Backoff Algorithm

Selectable Modiﬁed Backoff Algorithm or

standard backoff algorithm.

Only standard backoff algorithm available.

TX Descriptor Zero Buffer

Byte Count Capability

Allows TX buffer byte count of zero.

No capability for TX buffer byte count of zero.

Interframe Spacing (IFS)

Behavior

a) Implements two-part deferral after

transmit

b) Part 1 of two-part deferral after receive is

µs

c) Heartbeat window = 4

µs

d) Receive blind time after receive less than

500 ns

a) One-part deferral after transmit

b) Part 1 of two-part deferral after receive is

4.1

µs

c) Heartbeat window = 2

µs

d) Receive blind time after receive = 4.1

µs

“Heartbeat OK” (No CERR)

Deﬁnition

Heartbeat OK if collision is asserted at any

time from the beginning of the transmission

to the end of the heartbeat window.

Heartbeat OK if collision is asserted during

the heartbeat window.

Receive Lockup

Will not occur.

May occur when bus latency is large.

ALE Behavior

ALE may be driven HIGH at end of bus

mastership when ACON is set to 0. When

ACON is set to 1, ALE is not driven LOW at

end of bus mastership period.

ALE may be driven LOW at end of bus

mastership when ACON is set to 1. When

ACON is set to 0, ALE is not driven HIGH at

end of bus mastership period.

External Loopback on a Live

Network

No problems.

May receive invalid loopback failure

indications.

Software Reset (STOP Bit)

Handling

a) STOP bit in CSR0 is latched. When STOP

is set, the slave cycle is allowed to

complete before the C-LANCE resets.

b) CSR1 and CSR2 contents are preserved

when the STOP bit is set to one.

a) STOP bit in CSR0 not latched and will

reset the device immediately when

written.

b) CSR1 and CSR2 are not preserved when

the STOP bit is set to one.

CSR0 Slave Read Data

Stability

CSR0 latched during Slave reads to

guarantee timing on DAL lines.

CSR0 not latched during Slave read cycles

(could give timing violations on DAL lines).

INEA Bit Behavior

INEA bit can be set in CSR0 at any time,

regardless of the state of the STOP bit.

INEA cannot be set in CSR0 while the STOP

bit is set.

Effect of Setting the STOP

Bit on CSR0 Bits

Setting the STOP bit in CSR0 when the

STOP bit is already set does not affect any

of the other bits in CSR0 (they are not

cleared).

Setting the STOP bit in CSR0 causes all of

the other bits in CSR0 to clear, regardless of

the previous state of the STOP bit.

AC Speciﬁcation Changes

#06 (t

TEP) maximum = 60 ns

#08 (t

TDP) maximum = 60 ns

#18 (t

RDS) minimum = 35 ns

#30 (t

RDAS) minimum = 40 ns

#45 (t

RDYS) minimum = 65 ns

#06 (t

TEP) maximum = 70 ns

#08 (t

TDP) maximum = 70 ns

#18 (t

RDS) minimum = 40 ns

#30 (t

RDAS) minimum = 50 ns

#45 (t

RDYS) minimum = 75 ns

Burn-In Option

The burn-in option for the C-LANCE is no

longer available.

RX Descriptor Zero Buffer

Byte Count Handling

Unpredictable results when the RX

Descriptor Buffer Byte Count is set to zero.

Interprets a BCNT ﬁeld setting of zero in a

receive descriptor as a 4096-byte buffer.

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