AM79C90PC datasheet(1/62 Pages) AMD

部件名	AM79C90PC

功能描述	CMOS Local Area Network Controller for Ethernet (C-LANCE)

PDF	62 Pages

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制造商	AMD [Advanced Micro Devices]

网页	http://www.amd.com

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PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The

information is intended to help you evaluate this product. AMD reserves the right to change or discontinue

work on this proposed product without notice.

Publication# 17881

Rev: C Amendment/0

Issue Date: January 1998

1

Am79C90

CMOS Local Area Network Controller for Ethernet

(C-LANCE)

DISTINCTIVE CHARACTERISTICS

s Compatible with Ethernet and IEEE 802.3

10BASE-5 Type A, and 10BASE-2 Type B,

“Cheapernet,” 10BASE-T

s Easily interfaced with 80x86, 680x0, Am29000®,

Z8000™ microprocessors

s On-board DMA and buffer management, 64-byte

Receive, 48-byte Transmit FIFOs

s 24-bit-wide linear addressing (Bus Master Mode)

s Network and packet error reporting

s Back-to-back packet reception with as little as

0.5

µs interframe spacing

s Diagnostic Routines

— Internal/external loopback

— CRC logic check

— Time domain reﬂectometer

s Low power consumption for power-sensitive

applications

s Completely software- and hardware-compatible with

AMD’s LANCE device (Am7990) (see Appendix A)

GENERAL DESCRIPTION

The Am79C90 CMOS Local Area Network Controller

for Ethernet (C-LANCE) is a 48-pin VLSI device de-

signed to greatly simplify interfacing a microcomputer or

minicomputer to an IEEE 802.3/Ethernet Local Area

Network. The C-LANCE, in conjunction with the

Am7992B Serial Interface Adapter (SIA), Am7996 or

Am79C98 and Am79C100 Transceiver, and closely

coupled local memory and microprocessor, is intended

to provide the user with a complete interface module for

an Ethernet network. The Am79C90 is designed using

a scalable CMOS technology and is compatible with a

variety of microprocessors. On-board DMA, advanced

buffer management, and extensive error reporting and

diagnostics facilitate design and improve system

performance.

BLOCK DIAGRAM

INTR

HOLD

HLDA

ALE/AS

CS

ADR

DAS

DALO

DALI

READ

BM0/BYTE

BM1/BUSAKO

READY

RESET

Parallel

Bus

Interface

DMA/Data

Path Control

Microprogram

Store

C-LANCE/

CPU

Control

Bus

Interface

Station

Address

Detection

Retry

Logic

Serial I/O

Interface

A23:16

RX

RCLK

TX

TCLK

CLSN

TENA

RENA

DAL15:0

17881C-1

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