AM186ES-40VCW datasheet(36/102 Pages) AMD

36 / 102 page

Am186/188ES and Am186/188ESLV Microcontrollers

PRELIMIN ARY

S6/LOCK/CLKDIV2/PIO29

Bus Cycle Status Bit 6 (output, synchronous)

Bus Lock (output, synchronous)

Clock Divide by 2 (input, internal pullup)

S6—During the second and remaining periods of a

cycle (t2, t3, and t4), this pin is asserted High to indicate

a DMA-initiated bus cycle. During a bus hold or reset

condition, S6 floats.

LOCK—This signal is asserted Low to indicate to other

system bus masters that they are not to gain control of

the system bus. This signal is only available during t1.

LO CK

th e

Am1 86ES

and

Am18 8ES

microcontrollers does not conform to the timing of the

LOCK signal on the 80C186/188 microcontrollers. This

signal is primarily intended for use by emulators.

CLKDIV2—If S6/CLKDIV2/PIO29 is held Low during

power-on reset, the chip enters clock divided by 2

mode where the processor clock is derived by dividing

the external clock input by 2. If this mode is selected,

the PLL is disabled. The pin is sampled on the rising

edge of RES.

If S6 is to be used as PIO29 in input mode, the device

driving PIO29 must not drive the pin Low during power-

on reset. S6/CLKDIV2/PIO29 defaults to a PIO input

with pullup, so the pin does not need to be driven High

externally.

SRDY/PIO6

Synchronous Ready (input, synchronous,

level-sensitive)

This pin indicates to the microcontroller that the

addressed memory space or I/O device will complete a

data transfer. The SRDY pin accepts an active High

input synchronized to CLKOUTA.

Using SRDY instead of ARDY allows a relaxed system

timing because of the elimination of the one-half clock

period required to internally synchronize ARDY. To

a l ways a s se r t th e r eady co ndit i on t o th e

microcontroller, tie SRDY High. If the system does not

use SRDY, tie the pin Low to yield control to ARDY.

TMRIN0/PIO11

Timer Input 0 (input, synchronous, edge-sensitive)

This pin supplies a clock or control signal to the internal

microcontroller timer 0. After internally synchronizing a

Low-to-High transition on TMRIN0, the microcontroller

increments the timer. TMRIN0 must be tied High if not

being used. When PIO11 is enabled, TMRIN0 is pulled

High internally.

TMRIN0 is driven internally by INT2/INTA0/PWD when

pulse width demodulation mode is enabled. The

TMRIN0/PIO11 pin can be used as a PIO when pulse

width demodulation mode is enabled.

TMRIN1/PIO0

Timer Input 1 (input, synchronous, edge-sensitive)

This pin supplies a clock or control signal to the internal

microcontroller timer 1. After internally synchronizing a

Low-to-High transition on TMRIN1, the microcontroller

increments the timer. TMRIN1 must be tied High if not

being used. When PIO0 is enabled, TMRIN1 is pulled

High internally.

TMRIN1 is driven internally by INT2/INTA0/PWD when

pulse width demodulation mode is enabled. The

TMRIN1/PIO0 pin can be used as a PIO when pulse

width demodulation mode is enabled.

TMROUT0/PIO10

Timer Output 0 (output, synchronous)

This pin supplies the system with either a single pulse

or a continuous waveform with a programmable duty

cycle. TMROUT0 is floated during a bus hold or reset.

TMROUT1/PIO1

Timer Output 1 (output, synchronous)

This pin supplies the system with either a single pulse

or a continuous waveform with a programmable duty

cycle. TMROUT1 floats during a bus hold or reset.

TXD0/PIO22

Transmit Data 0 (output, asynchronous)

This pin supplies asynchronous serial transmit data to

the system from serial port 0.

TXD1/PIO27

Transmit Data 1 (output, asynchronous)

This pin supplies asynchronous serial transmit data to

the system from serial port 1.

UCS/ONCE1

Upper Memory Chip Select (output, synchronous)

ONCE Mode Request 1 (input, internal pullup)

UCS—This pin indicates to the system that a memory

access is in progress to the upper memory block. The

base address and size of the upper memory block are

programmable up to 512 Kbytes. UCS is held High

during a bus hold condition.

After reset, UCS is active for the 64 Kbyte memory

range from F0000h to FFFFFh, including the reset

address of FFFF0h.

ONCE1—During reset, this pin and LCS/ONCE0 indi-

cate to the microcontroller the mode in which it should

operate. ONCE0 and ONCE1 are sampled on the ris-

ing edge of RES. If both pins are asserted Low, the mi-

crocontroller enters ONCE mode. Otherwise, it

operates normally. In ONCE mode, all pins assume a

high-impedance state and remain in that state until a

subsequent reset occurs. To guarantee that the micro-

AM186ES-40VCW 数据表(PDF) 36 Page - Advanced Micro Devices

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