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AM186ES-40VCW 数据表(PDF) 74 Page - Advanced Micro Devices |
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AM186ES-40VCW 数据表(HTML) 74 Page - Advanced Micro Devices |
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74 / 102 page  74 Am186/188ES and Am186/188ESLV Microcontrollers PRELIMIN ARY SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges PSRAM Read Cycle (20 MHz and 25 MHz) Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC –0.5 V. a Testing is performed with equal loading on referenced pins. b If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. Parameter Preliminary Unit 20 MHz 25 MHz No. Symbol Description Min Max Min Max General Timing Requirements 1tDVCL Data in Setup 10 10 ns 2tCLDX Data in Hold(b) 33 ns General Timing Responses 5tCLAV AD Address Valid Delay and BHE 0 25 0 20 ns 7tCLDV Data Valid Delay 0 25 0 20 ns 8tCHDX Status Hold Time 0 0 ns 9tCHLH ALE Active Delay 25 20 ns 10 tLHLL ALE Width tCLCL–10=40 tCLCL–10=30 ns 11 tCHLL ALE Inactive Delay 25 20 ns 23 tLHAV ALE High to Address Valid 20 15 ns 80 tCLCLX LCS Inactive Delay 0 25 0 20 ns 81 tCLCSL LCS Active Delay 0 25 0 20 ns 84 tLRLL LCS Precharge Pulse Width tCLCL+ tCLCH–3 tCLCL + tCLCH –3 ns Read Cycle Timing Responses 24 tAZRL AD Address Float to RD Active 0 0 ns 25 tCLRL RD Active Delay 0 25 0 20 ns 26 tRLRH RD Pulse Width 2tCLCL–15=85 2tCLCL–15=65 ns 27 tCLRH RD Inactive Delay 0 25 0 20 ns 28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–3 ns 59 tRHDX RD High to Data Hold on AD Bus(b) 00 ns 66 tAVRL A Address Valid to RD Low tCLCL+ tCHCL–3 tCLCL+ tCHCL–3 ns 68 tCHAV CLKOUTA High to A Address Valid 025020 ns |
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