AM186ES-40VCW datasheet(45/102 Pages) AMD

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Am186/188ES and Am186/188ESLV Microcontrollers

P R E L IMINA R Y

External Source Clock

Alternately, the internal oscillator can be driven from an

external clock source. This source should be con-

nected to the input of the inverting amplifier (X1), with

the output (X2) not connected.

System Clocks

The base system clock of AMD’s original 80C186 and

80C188 microcontrollers is renamed CLKOUTA and

the additional output is called CLKOUTB. CLKOUTA

and CLKOUTB operate at either the processor fre-

quency or the PLL frequency. The output drivers for

both clocks are individually programmable for disable.

Figure 9 shows the organization of the clocks.

The second clock output (CLKOUTB) allows one clock

to run at the PLL frequency and the other clock to run

at the power-save frequency. Individual drive enable

bits allow selective enabling of just one or both of these

clock outputs.

Power-Save Operation

The power-save mode of the Am186ES and Am188ES

microcontrollers reduces power consumption and heat

dissipation, thereby extending battery life in portable

systems. In power-save mode, operation of the CPU

and internal peripherals continues at a slower clock fre-

quency. When an interrupt occurs, the microcontroller

automatically returns to its normal operating frequency

on the internal clock’s next rising edge of t3.

Note: Power-save operation requires that clock-de-

pendent devices be reprogrammed for clock frequency

changes. Software drivers must be aware of clock fre-

quency.

Initialization and Processor Reset

Processor initialization or startup is accomplished by

driving the RES input pin Low. RES must be held Low

for 1 ms during power-up to ensure proper device ini-

tialization. RES forces the Am186ES and Am188ES

microcontrollers to terminate all execution and local

bus activity. No instruction or bus activity occurs as long

as RES is active. After RES becomes inactive and an

internal processing interval elapses, the microcontrol-

ler begins execution with the instruction at physical lo-

cation FFFF0h, with UCS asserted with three wait

states. RES also sets some registers to predefined val-

ues and resets the watchdog timer.

The Reset Configuration Register

When the RES input is asserted Low, the contents of

the address/data bus (AD15–AD0) are written into the

reset configuration register. The system can place con-

figuration information on the address/data bus using

weak external pullup or pulldown resistors, or using an

external driver that is enabled during reset. The pro-

cessor does not drive the address/data bus during re-

set.

For example, the reset configuration register could be

used to provide the software with the position of a con-

figuration switch in the system. Using weak external

pullup and pulldown resistors on the address and data

bus, the system can provide the microcontroller with a

value corresponding to the position of the jumper dur-

ing a reset.

Figure 9.

Clock Organization

PLL

Power-Save

Divisor

(/2 to /128)

Mux

CLKOUTA

CLKOUTB

Drive

Enable

Drive

Enable

X1, X2

Processor Internal Clock

Time

Delay

6 ± 2.5ns

Mux

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