AM186ES-40VCW datasheet(37/102 Pages) AMD

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Am186/188ES and Am186/188ESLV Microcontrollers

P R E L IMINAR Y

controller does not inadvertently enter ONCE mode,

ONCE1 has a weak internal pullup resistor that is ac-

tive only during a reset. This pin is not three-stated dur-

ing a bus hold condition.

UZI/PIO26

Upper Zero Indicate (output, synchronous)

This pin lets the designer determine if an access to the

interrupt vector table is in progress by ORing it with bits

15–10 of the address and data bus (AD15–AD10 on

the 186 and AO15–AO10 on the 188). UZI is the logical

OR of the inverted A19–A16 bits. It asserts in the first

period of a bus cycle and is held throughout the cycle.

This pin should be allowed to float or it should be pulled

High at reset. This pin has an internal pullup. If this pin

is Low at the negation of reset, the Am186ES and

Am188ES microcontrollers will enter a reserved clock

test mode.

VCC

Power Supply (input)

These pins supply power (+5 V) to the microcontroller.

WHB (Am186ES Microcontroller Only)

Write High Byte (output, three-state, synchronous)

This pin and WLB indicate to the system which bytes of

the data bus (upper, lower, or both) participate in a

write cycle. In 80C186 microcontroller designs, this

information is provided by BHE, AD0, and WR.

However, by using WHB and WLB, the standard

system interface logic and external address latch that

were required are eliminated.

WHB is asserted with AD15–AD8. WHB is the logical

OR of BHE and WR. This pin floats during reset.

WLB (Am186ES Microcontroller Only)

WB (Am188ES Microcontroller Only)

Write Low Byte (output, three-state, synchronous)

Write Byte (output, three-state, synchronous)

WLB—This pin and WHB indicate to the system which

bytes of the data bus (upper, lower, or both) participate

in a write cycle. In 80C186 microcontroller designs, this

information is provided by BHE, AD0, and WR.

However, by using WHB and WLB, the standard

system interface logic and external address latch that

were required are eliminated.

WLB is asserted with AD7–AD0. WLB is the logical OR

of AD0 and WR. This pin floats during reset.

WB—On the Am188ES microcontroller, this pin

indicates a write to the bus. WB uses the same early

timing as the nonmultiplexed address bus. WB is

associated with AD7–AD0. This pin floats during reset.

Write Strobe (output, synchronous)

WR—This pin indicates to the system that the data on

the bus is to be written to a memory or I/O device. WR

floats during a bus hold or reset condition.

Crystal Input (input)

This pin and the X2 pin provide connections for a

fundamental mode or third-overtone, parallel-resonant

crystal used by the internal oscillator circuit. To provide

the microcontroller with an external clock source,

connect the source to the X1 pin and leave the X2 pin

unconnected.

Crystal Output (output)

This pin and the X1 pin provide connections for a

fundamental mode or third-overtone, parallel-resonant

crystal used by the internal oscillator circuit. To provide

the microcontroller with an external clock source, leave

the X2 pin unconnected and connect the source to the

X1 pin.

AM186ES-40VCW 数据表(PDF) 37 Page - Advanced Micro Devices

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