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AM186ES-40VCW 数据表(PDF) 77 Page - Advanced Micro Devices

部件名 AM186ES-40VCW
功能描述  High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers
PDF  102 Pages
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

AM186ES-40VCW 数据表(HTML) 77 Page - Advanced Micro Devices

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Am186/188ES and Am186/188ESLV Microcontrollers
77
P R E L IMINAR Y
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
PSRAM Write Cycle (20 MHz and 25 MHz)
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL=50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, WR, WHB, and WLB signals.
Parameter
Preliminary
Unit
20 MHz
25 MHz
No.
Symbol
Description
Min
Max
Min
Max
General Timing Responses
5tCLAV
AD Address Valid Delay and BHE
0
25
0
20
ns
7tCLDV
Data Valid Delay
0
25
0
20
ns
8tCHDX
Status Hold Time
0
0
ns
9tCHLH
ALE Active Delay
25
20
ns
10
tLHLL
ALE Width
tCLCL–10=40
tCLCL–10=30
ns
11
tCHLL
ALE Inactive Delay
25
20
ns
20
tCVCTV
Control Active Delay 1(b)
0
25
0
20
ns
23
tLHAV
ALE High to Address Valid
20
15
ns
80
tCLCLX
LCS Inactive Delay
0
25
0
20
ns
81
tCLCSL
LCS Active Delay
0
25
0
20
ns
84
tLRLL
LCS Precharge Pulse Width
tCLCL + tCLCH –3
tCLCL + tCLCH –3
Write Cycle Timing Responses
30
tCLDOX
Data Hold Time
0
0
ns
31
tCVCTX
Control Inactive Delay(b)
0
25
0
20
ns
32
tWLWH
WR Pulse Width
2tCLCL–10=90
2tCLCL–10=70
ns
33
tWHLH
WR Inactive to ALE High(a)
tCLCH–2
tCLCH–2
ns
34
tWHDX
Data Hold after WR(a)
tCLCL–10=40
tCLCL–10=30
ns
65
tAVWL
A Address Valid to WR Low
tCLCL+tCHCL
–3
tCLCL+tCHCL
–3
ns
68
tCHAV
CLKOUTA High to A
Address Valid
0
25
0
20
ns
87
tAVBL
A Address Valid to WHB, WLB
Low
tCHCL–3
25
tCHCL–3
20
ns



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