AM186ES-40VCW datasheet(42/102 Pages) AMD

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Am186/188ES and Am186/188ESLV Microcontrollers

PRELIMINA R Y

Table 6.

Programming Am186ES Microcontroller

Bus Width

Byte-Write Enables

The Am186ES microcontroller provides the WHB

(Write High Byte) and WLB (Write Low Byte) signals,

which act as byte-write enables.

WHB is the logical OR of BHE and WR. WHB is Low

when BHE and WR are both Low. WLB is the logical

OR of A0 and WR. WLB is Low when A0 and WR are

both Low. WB is Low whenever a byte is written on the

Am188ES microcontroller.

On the Am188ES microcontroller, the WB (Write Byte)

pin indicates a write to the bus. WB uses the same

early timing as the nonmulitplexed address bus. WB is

associated with AD7–-AD0. This pin floats during reset.

The byte-write enables are driven in conjunction with

the nonmultiplexed address bus as required for the

write timing requirements of common SRAMs.

Pseudo Static RAM (PSRAM) Support

The Am186ES and Am188ES microcontrollers support

the use of PSRAM devices in low memory chip-select

(LCS) space only. When PSRAM mode is enabled, the

timing for the LCS signal is modified by the chip-select

control unit to provide a CS precharge period during

PS R A M access e s . T h e 40 - M Hz timing of t h e

Am186ES and Am188ES microcontrollers is appropri-

ate to allow 70-ns PSRAM to run with one wait state.

PSRAM mode is enabled through a bit in the Low Mem-

ory Chip-Select (LMCS) register. The PSRAM feature

is disabled on CPU reset.

In addition to the LCS timing changes for PSRAM pre-

charge, the PSRAM devices also require periodic re-

fresh of all internal row addresses to retain their data.

Although refresh of PSRAM can be accomplished sev-

eral ways, the Am186ES and Am188ES microcontrol-

lers implement auto refresh only.

The Am186ES and Am188ES microcontrollers gener-

ate a refresh signal, RFSH, to the PSRAM devices

when PSRAM mode and the refresh control unit are

enabled. No refresh address is required by the PSRAM

when using the auto refresh mechanism. The RFSH

signal is multiplexed with the MCS3 signal pin. When

PSRAM mode is enabled, MCS3 is not available for

use as a chip-select signal.

The refresh control unit must be programmed before

accessing PSRAM in LCS space. The refresh counter

in the clock prescaler (CDRAM) register must be con-

figured with the required refresh interval value. The

ending address of LCS space and the ready and wait-

state generation in the LMCS register must also be pro-

grammed. The refresh counter reload value in the

CDRAM register should not be set to less than 18 (12h)

in order to provide time for processor cycles within re-

fresh. The refresh address counter must be set to

000000h to prevent another chip select from asserting.

LCS is held High during a refresh cycle. The A bus is

not used during refresh cycles. The LMCS register

must be configured to external ready ignored (R2=1)

with one wait state (R1–R0=01b), and the PSRAM

mode enable bit (PSE) must be set to 1.

PERIPHERAL CONTROL BLOCK (PCB)

The integrated peripherals of the Am186ES and

Am188ES microcontrollers are controlled by 16-bit

read/write registers. The peripheral registers are con-

tained within an internal 256-byte control block. The

registers are physically located in the peripheral de-

vices they control, but they are addressed as a single

256-byte block. Table 7 shows a map of these regis-

ters.

Reading and Writing the PCB

Code that is intended to execute on the Am188ES mi-

crocontroller should perform all writes to the PCB reg-

isters as byte writes. These writes transfer 16 bits of

data to the PCB register even if an 8-bit register is

named in the instruction. For example, out dx, al results

in the value of ax being written to the port address in dx.

Reads to the PCB should be done as word reads. Code

written in this manner runs correctly on the Am188ES

microcontroller and on the Am186ES microcontroller.

Unaligned reads and writes to the PCB result in unpre-

dictable behavior on both the Am186ES and Am188ES

microcontrollers.

For a complete description of all the registers in the

PCB, see the

Am186ES and Am188ES Microcontrol-

lers User’s Manual, order# 21096.

Space

AUXCON

Field

Value

Bus

Width

Comments

UCS

–

16 bits

not

configurable

LCS

LSIZ

16 bits

default

8 bits

I/O

IOSIZ

16 bits

default

8 bits

Other

MSIZ

16 bits

default

8 bits

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