DAC5687IPZP datasheet(32/79 Pages) TI

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Serial Interface

DAC5687

SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006

The serial port of the DAC5687 is a flexible serial interface which communicates with industry standard

microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the

operating modes of the DAC5687. It is compatible with most synchronous transfer formats and can be configured

as a three- or four-pin interface by sif_4pin in register CONFIG3. In both configurations, SCLK is the serial

interface input clock and SDENB is serial interface enable. For three-pin configuration, SDIO is a bidirectional pin

for both data in and data out. For four-pin configuration, SDIO is data in only and SDO is data out only.

Each read/write operation is framed by signal SDENB (serial data enable bar) asserted low for 2 to 5 bytes,

depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle, which

identifies the following data transfer cycle as read or write, how many bytes to transfer, and what address to

transfer the data. Table 6 indicates the function of each bit in the instruction cycle and is followed by a detailed

description of each bit. Frame bytes 2 to 5 comprise the data transfer cycle.

Table 6. Instruction Byte of the Serial Interface

MSB

LSB

Bit

Description

R/W

Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation

from the DAC5687, and a low indicates a write operation to the DAC5687.

[N1:N0] Identifies the number of data bytes to be transferred, per Table 7. Data is transferred MSB first. With

multibyte transfers, [A4:A0] is the address of the first data byte, and the address is decremented for each

subsequent byte.

Table 7. Number of Transferred Bytes Within One

Communication Frame

Description

Transfer 1 Byte

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

[A4:A0] Identifies the address of the register to be accessed during the read or write operation. For multibyte

transfers, this address is the starting address. Note that the address is written to the DAC5687 MSB first.

Figure 33 shows the serial interface timing diagram for a DAC5687 write operation. SCLK is the serial interface

clock input to the DAC5687. Serial data enable SDENB is an active-low input to the DAC5687. SDIO is serial

data in. Input data to the DAC5687 is clocked on the rising edges of SCLK.

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