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DAC5687

SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006

• First sentence: Changed "The lower limit" to "upper limit". 3rd sentence: "upper limit" to "lower limit". Last sentence:

"Exceeding the upper limit" to "Exceeding the limits". ........................................................................................................... 6

• Noise Floor Test Conditions: Swapped "CLK1 = 122.88 MHz" and "CLK2 = 491.52 MHz" for all four lines........................ 9

• Input data rate, External or dual-clock modes, minimum changed to 0 Hz........................................................................... 9

• Input data rate, PLL clock mode, minimum changed to 2.5 MHz.......................................................................................... 9

• VCO maximum frequency test condition, "pll_kv = 0" changed to "pll_kv = 1" and vice versa........................................... 10

• VCO minimum frequency test condition, "pll_kv = 0" changed to "pll_kv = 1" and vice versa............................................ 10

• Figure 26 – "16702A Pattern Generator Card" changed to "16720A Pattern Generator Card" .......................................... 18

• Figure 27 – "16702A Pattern Generator Card" changed to "16720A Pattern Generator Card" .......................................... 19

• Figure 45: changed "CLK2" to "CLK1"................................................................................................................................. 42

• Second paragraph of Analog Current Outputs reworded .................................................................................................... 52

• Table 15: "pll_kv = 0" changed to "pll_kv = 1" and vice versa ............................................................................................ 57

• Figure 72 caption – changed "X4 and X4L" to "X8" ............................................................................................................ 61

• Figure 81 – removed one stage of interpolation from DAC block diagram ......................................................................... 70

• Added thermal pad dimensions ............................................................................................................................................. 1

• Reversed "External Clock Mode" and "PLL Clock Mode" in noise floor test......................................................................... 9

• Changed PLLLOCK Output Signal for PLLVDD = 0 to "Normal Operation" in Table 5 ...................................................... 31

• Reversed t

• Reversed t

• Reversed t

• Updated Figure 46 ............................................................................................................................................................... 42

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