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DAC5687IPZP 数据表(PDF) 24 Page - Texas Instruments |
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DAC5687IPZP 数据表(HTML) 24 Page - Texas Instruments |
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24 / 79 page  www.ti.com Programming Registers Register Name: VERSION—Address: 0x00, Default = 0x03 DAC5687 SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006 REGISTER MAP Bit 7 Bit 0 Name Address Default Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (MSB) (LSB) VERSION 0x00 0x03 sleep_daca sleep_dacb hpla hplb unused version(2:0) CONFIG0 0x01 0x00 pll_div(1:0) pll_freq pll_kv interp(1:0) inv_plllock fifo_bypass CONFIG1 0x02 0x00 qflag interl dual_clk twos rev_abus rev_bbus fir_bypass full_bypass CONFIG2 0x03 0x80 nco nco_gain qmc cm_mode(3:0) invsinc CONFIG3 0x04 0x00 sif_4pin dac_ser_dat half_rate unused usb counter_mode(2:0) a SYNC_CNTL 0x05 0x00 sync_phstr sync_nco sync_cm sync_fifo(2:0) unused unused SER_DATA_0 0x06 0x00 dac_data(7:0) SER_DATA_1 0x07 0x00 dac_data(15:8) Factory use only 0x08 0x00 NCO_FREQ_0 0x09 0x00 freq(7:0) NCO_FREQ_1 0x0A 0x00 freq(15:8) NCO_FREQ_2 0x0B 0x00 freq(23:16) NCO_FREQ_3 0x0C 0x40 freq(31:24) NCO_PHASE_0 0x0D 0x00 phase(7:0) NCO_PHASE_1 0x0E 0x00 phase(15:8) DACA_OFFSET_0 0x0F 0x00 daca_offset(7:0) DACB_OFFSET_0 0x10 0x00 dacb_offset(7:0) DACA_OFFSET_1 0x11 0x00 daca_offset(12:8) unused unused unused DACB_OFFSET_1 0x12 0x00 dacb_offset(12:8) unused unused unused QMCA_GAIN_0 0x13 0x00 qmc_gain_a(7:0) QMCB_GAIN_0 0x14 0x00 qmc_gain_b(7:0) QMC_PHASE_0 0x15 0x00 qmc_phase(7:0) QMC_PHASE_GAIN_1 0x16 0x00 qmc_phase(9:8) qmc_gain_a(10:8) qmc_gain_b(10:8) DACA_GAIN_0 0x17 0x00 daca_gain(7:0) DACB_GAIN_0 0x18 0x00 dacb_gain(7:0) DACA_DACB_GAIN_1 0x19 0xFF daca_gain(11:8) dacb_gain(11:8) Factory use only 0x1A 0x00 ATEST 0x1B 0x00 atest(4:0) phstr_del(1:0) unused DAC_TEST 0x1C 0x00 factory use only phstr_clkdiv_sel Factory use only 0x1D 0x00 Factory use only 0x1E 0x00 Factory use only 0x1F 0x00 BIT 7 BIT 0 sleep_daca sleep_dacb hpla hplb unused version(2:0) 0 0 0 0 0 0 1 1 sleep_daca: DAC A sleeps when set, operational when cleared. sleep_dacb: DAC B sleeps when set, operational when cleared. hpla: A-side first FIR filter in high-pass mode when set, low-pass mode when cleared. hplb: B-side first FIR filter in high-pass mode when set, low-pass mode when cleared. version(2:0): A hardwired register that contains the version of the chip. Read-only. 24 Submit Documentation Feedback Copyright © 2005–2006, Texas Instruments Incorporated Product Folder Link(s): DAC5687 |
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