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DAC5687IPZP 数据表(PDF) 62 Page - Texas Instruments

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部件名 DAC5687IPZP
功能描述  16-BIT, 500 MSPS 2?? INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)
PDF  79 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DAC5687IPZP 数据表(HTML) 62 Page - Texas Instruments

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(a) X2 Mode
(b) X4L Mode
fDAC − MHz
0
10
20
30
40
50
60
70
80
90
0
100
200
300
400
500
G032
fDAC/2
fDAC − MHz
0
10
20
30
40
50
60
70
80
90
100
0
100
200
300
400
500
G033
fDAC/2
fDAC/4
(c) X4 Mode
(d) X8 Mode
fDAC − MHz
0
10
20
30
40
50
60
70
80
90
100
0
100
200
300
400
500
G034
fDAC/2
fDAC/4
fDAC x 3/4
fDAC − MHz
0
10
20
30
40
50
60
70
80
90
100
0
100
200
300
400
500
G035
fDAC/2
fDAC/4
fDAC x 3/4
fDAC/8
fDAC x 7/8
DAC5687
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
Figure 73 and Figure 74 show the typical worst-case spurious signal amplitudes vs fDAC for a signal frequency
fSIG = 11 × fDAC/32 in each mode for PLL on (PLL clock mode) and PLL off (external and dual-clock modes).
Each spurious signal (fDAC/2, fDAC/4 and fDAC/8) has its own curve. The spurious signal amplitudes can then be
adjusted for the exact signal frequency fSIG by applying the amplitude adjustment factor shown in Figure 75. The
amplitude adjustment factor is the same for each spurious signal (fDAC/2, fDAC/4, and fDAC/8) and is normalized for
fSIG = 11 × fDAC/32.
Figure 73. Clock-Related Spurious Signal Amplitude With PLL Off for fSIG = 11 × fDAC / 32
62
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Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Link(s): DAC5687



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