I2CCON datasheet(77/210 Pages) MICROCHIP

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DS70139G-page 77

dsPIC30F2011/2012/3012/3013

10.0

TIMER2/3 MODULE

This section describes the 32-bit general purpose

Timer module (Timer2/3) and associated Operational

modes. Figure 10-1 depicts the simplified block

diagram of the 32-bit Timer2/3 module. Figure 10-2

and Figure 10-3 show Timer2/3 configured as two

independent

16-bit

timers,

Timer2

and

Timer3,

respectively.

The Timer2/3 module is a 32-bit timer (which can be

configured as two 16-bit timers) with selectable

operating modes. These timers are utilized by other

peripheral modules, such as:

• Input Capture

• Output Compare/Simple PWM

The following sections provide a detailed description,

including setup and Control registers, along with

associated block diagrams for the operational modes of

the timers.

The 32-bit timer has the following modes:

• Two independent 16-bit timers (Timer2 and

Timer3) with all 16-bit operating modes (except

Asynchronous Counter mode)

• Single 32-bit timer operation

• Single 32-bit synchronous counter

Further, the following operational characteristics are

supported:

• ADC event trigger

• Timer gate operation

• Selectable prescaler settings

• Timer operation during Idle and Sleep modes

• Interrupt on a 32-bit period register match

These operating modes are determined by setting the

appropriate bit(s) in the 16-bit T2CON and T3CON

SFRs.

For 32-bit timer/counter operation, Timer2 is the ls word

and Timer3 is the ms word of the 32-bit timer.

16-bit Timer Mode: In the 16-bit mode, Timer2 and

Timer3 can be configured as two independent 16-bit

timers. Each timer can be set up in either 16-bit Timer

mode or 16-bit Synchronous Counter mode. See

Section 9.0 “Timer1 Module” for details on these two

operating modes.

The only functional difference between Timer2 and

Timer3 is that Timer2 provides synchronization of the

clock prescaler output. This is useful for high frequency

external clock inputs.

32-bit Timer Mode: In the 32-bit Timer mode, the timer

increments on every instruction cycle, up to a match

value preloaded into the combined 32-bit Period

count.

For synchronous 32-bit reads of the Timer2/Timer3

pair, reading the ls word (TMR2 register) causes the ms

word to be read and latched into a 16-bit holding

For synchronous 32-bit writes, the holding register

(TMR3HLD) must first be written to. When followed by

a write to the TMR2 register, the contents of TMR3HLD

is transferred and latched into the MSB of the 32-bit

timer (TMR3).

32-bit Synchronous Counter Mode: In the 32-bit

Synchronous Counter mode, the timer increments on

the rising edge of the applied external clock signal

which is synchronized with the internal phase clocks.

The timer counts up to a match value preloaded in the

combined 32-bit period register, PR3/PR2, then resets

to ‘0’ and continues.

When the timer is configured for the Synchronous

Counter mode of operation and the CPU goes into the

Idle mode, the timer stops incrementing unless the

TSIDL bit (T2CON<13>) = 0. If TSIDL = 1, the timer

module logic resumes the incrementing sequence

upon termination of the CPU Idle mode.

Note:

This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals,

descriptions

and

general device functionality, refer to the

“dsPIC30F Family Reference Manual

“(DS70046).

Note:

For 32-bit timer operation, T3CON control

bits are ignored. Only T2CON control bits

are used for setup and control. Timer2

clock and gate inputs are utilized for the

32-bit timer module, but an interrupt is

generated with the Timer3 interrupt flag

(T3IF) and the interrupt is enabled with the

Timer3 interrupt enable bit (T3IE).

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