I2CCON datasheet(84/210 Pages) MICROCHIP

84 / 210 page

dsPIC30F2011/2012/3012/3013

DS70139G-page 84

11.1.2

CAPTURE BUFFER OPERATION

Each capture channel has an associated FIFO buffer

which is four 16-bit words deep. There are two status

flags which provide status on the FIFO buffer:

• ICBNE – Input Capture Buffer Not Empty

• ICOV – Input Capture Overflow

The ICBNE is set on the first input capture event and

remains set until all capture events have been read

from the FIFO. As each word is read from the FIFO, the

remaining words are advanced by one position within

the buffer.

In the event that the FIFO is full with four capture

events, and a fifth capture event occurs prior to a read

of the FIFO, an overflow condition occurs and the ICOV

bit is set to a logic ‘1’. The fifth capture event is lost and

is not stored in the FIFO. No additional events are

captured until all four events have been read from the

buffer.

If a FIFO read is performed after the last read and no

new capture event has been received, the read will

yield indeterminate results.

11.1.3

TIMER2 AND TIMER3 SELECTION

MODE

The input capture module consists of up to 8 input

capture channels. Each channel can select between

one of two timers for the time base, Timer2 or Timer3.

Selection of the timer resource is accomplished

through SFR bit, ICTMR (ICxCON<7>). Timer3 is the

default timer resource available for the input capture

module.

11.1.4

HALL SENSOR MODE

When the input capture module is set for capture on

every edge, rising and falling, ICM<2:0> = 001, the

following operations are performed by the input capture

logic:

• The input capture interrupt flag is set on every

edge, rising and falling.

• The interrupt on Capture mode setting bits,

ICI<1:0>, is ignored since every capture

generates an interrupt.

• A capture overflow condition is not generated in

this mode.

11.2

Input Capture Operation During

Sleep and Idle Modes

An input capture event generates a device wake-up or

interrupt, if enabled, if the device is in CPU Idle or Sleep

mode.

Independent of the timer being enabled, the input

capture module wakes up from the CPU Sleep or Idle

mode when a capture event occurs if ICM<2:0> = 111

and the interrupt enable bit is asserted. The same

wake-up can generate an interrupt if the conditions for

processing

the

interrupt

have

been

satisfied.

The wake-up feature is useful as a method of adding

extra external pin interrupts.

11.2.1

INPUT CAPTURE IN CPU SLEEP

MODE

CPU Sleep mode allows input capture module

operation with reduced functionality. In the CPU Sleep

mode, the ICI<1:0> bits are not applicable and the input

capture module can only function as an external

interrupt source.

The capture module must be configured for interrupt

only on rising edge (ICM<2:0> = 111) in order for the

input capture module to be used while the device is in

Sleep mode. The prescale settings of 4:1 or 16:1 are

not applicable in this mode.

11.2.2

INPUT CAPTURE IN CPU IDLE

MODE

CPU Idle mode allows input capture module operation

with full functionality. In the CPU Idle mode, the Interrupt

mode selected by the ICI<1:0> bits is applicable, as well

as the 4:1 and 16:1 capture prescale settings which are

defined by control bits ICM<2:0>. This mode requires

the selected timer to be enabled. Moreover, the ICSIDL

bit must be asserted to a logic ‘0’.

the

input

capture

module

defined

ICM<2:0> = 111 in CPU Idle mode, the input capture

pin serves only as an external interrupt pin.

11.3

Input Capture Interrupts

The input capture channels have the ability to generate

an interrupt based on the selected number of capture

events. The selection number is set by control

bits, ICI<1:0> (ICxCON<6:5>).

Each channel provides an interrupt flag (ICxIF) bit. The

respective capture channel interrupt flag is located in

the corresponding IFSx register.

Enabling

interrupt

accomplished

via

the

respective capture channel interrupt enable (ICxIE) bit.

The capture interrupt enable bit is located in the

corresponding IEC Control register.

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