I2CCON datasheet(100/210 Pages) MICROCHIP

100 / 210 page

dsPIC30F2011/2012/3012/3013

DS70139G-page 100

14.4.1

10-BIT MODE SLAVE

TRANSMISSION

Once a slave is addressed in this fashion with the full

10-bit address (we will refer to this state as

“PRIOR_ADDR_MATCH”), the master can begin

sending data bytes for a slave reception operation.

14.4.2

10-BIT MODE SLAVE RECEPTION

Once addressed, the master can generate a Repeated

Start, reset the high byte of the address and set the

R_W bit without generating a Stop bit, thus initiating a

slave transmit operation.

14.5

Automatic Clock Stretch

In the Slave modes, the module can synchronize buffer

reads and write to the master device by clock stretching.

14.5.1

TRANSMIT CLOCK STRETCHING

Both 10-bit and 7-bit Transmit modes implement clock

stretching by asserting the SCLREL bit after the falling

edge of the ninth clock, if the TBF bit is cleared,

indicating the buffer is empty.

In Slave Transmit modes, clock stretching is always

performed irrespective of the STREN bit.

Clock synchronization takes place following the ninth

clock of the transmit sequence. If the device samples

an ACK on the falling edge of the ninth clock and if the

TBF bit is still clear, then the SCLREL bit is

automatically cleared. The SCLREL being cleared to

‘0’ will assert the SCL line low. The user’s ISR must set

the SCLREL bit before transmission is allowed to

continue. By holding the SCL line low, the user has time

to service the ISR and load the contents of the I2CTRN

before the master device can initiate another transmit

sequence.

14.5.2

RECEIVE CLOCK STRETCHING

The STREN bit in the I2CCON register can be used to

enable clock stretching in Slave Receive mode. When

the STREN bit is set, the SCL pin will be held low at the

end of each data receive sequence.

14.5.3

CLOCK STRETCHING DURING

7-BIT ADDRESSING (STREN = 1)

When the STREN bit is set in Slave Receive mode, the

SCL line is held low when the buffer register is full. The

method for stretching the SCL output is the same for

both 7 and 10-bit addressing modes.

Clock stretching takes place following the ninth clock of

the receive sequence. On the falling edge of the ninth

clock at the end of the ACK sequence, if the RBF bit is

set, the SCLREL bit is automatically cleared, forcing

the SCL output to be held low. The user’s ISR must set

the SCLREL bit before reception is allowed to continue.

By holding the SCL line low, the user has time to

service the ISR and read the contents of the I2CRCV

before the master device can initiate another receive

sequence. This will prevent buffer overruns from

occurring.

14.5.4

CLOCK STRETCHING DURING

10-BIT ADDRESSING (STREN = 1)

Clock stretching takes place automatically during the

addressing sequence. Because this module has a

the protocol to wait for the address to be updated.

After the address phase is complete, clock stretching

will occur on each data receive or transmit sequence as

was described earlier.

14.6

Software Controlled Clock

Stretching (STREN = 1)

When the STREN bit is ‘1’, the SCLREL bit may be

cleared by software to allow software to control the

clock stretching. The logic will synchronize writes to the

SCLREL bit with the SCL clock. Clearing the SCLREL

bit will not assert the SCL output until the module

detects a falling edge on the SCL output and SCL is

sampled low. If the SCLREL bit is cleared by the user

while the SCL line has been sampled low, the SCL

output will be asserted (held low). The SCL output will

remain low until the SCLREL bit is set, and all other

devices on the I2C bus have de-asserted SCL. This

ensures that a write to the SCLREL bit will not violate

the minimum high time requirement for SCL.

If the STREN bit is ‘0’, a software write to the SCLREL

bit will be disregarded and have no effect on the

SCLREL bit.

Note 1: If the user loads the contents of I2CTRN,

setting the TBF bit before the falling edge

of the ninth clock, the SCLREL bit will not

be cleared and clock stretching will not

occur.

2: The SCLREL bit can be set in software,

regardless of the state of the TBF bit.

Note 1: If the user reads the contents of the

I2CRCV, clearing the RBF bit before the

falling edge of the ninth clock, the

SCLREL bit will not be cleared and clock

stretching will not occur.

2: The SCLREL bit can be set in software

regardless of the state of the RBF bit. The

user should be careful to clear the RBF

bit in the ISR before the next receive

sequence in order to prevent an overflow

condition.

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