I2CCON datasheet(93/210 Pages) MICROCHIP

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DS70139G-page 93

dsPIC30F2011/2012/3012/3013

13.0

SPI™ MODULE

The Serial Peripheral Interface (SPI™) module is a

synchronous

serial

interface.

useful

for

communicating with other peripheral devices, such as

EEPROMs, shift registers, display drivers and A/D

converters, or other microcontrollers. It is compatible

with

Motorola's

SPI

and

SIOP

interfaces.

The

dsPIC30F2011/2012/3012/3013 devices feature one

SPI module, SPI1.

13.1

Operating Function Description

Figure 13-1 is a simplified block diagram of the SPI

module, which consists of a 16-bit shift register,

SPI1SR, used for shifting data in and out, and a buffer

shown) configures the module. Additionally, status

conditions.

Four I/O pins comprise the serial interface:

• SDI1 (serial data input)

• SDO1 (serial data output)

• SCK1 (shift clock input or output)

• SS1 (active-low slave select).

In Master mode operation, SCK1 is a clock output. In

Slave mode, it is a clock input.

A series of eight (8) or sixteen (16) clock pulses shift

out

bits

from

the

SPI1SR

SDO1

and

simultaneously shift in data from SDI1 pin. An interrupt

is generated when the transfer is complete and the

interrupt flag bit (SPI1IF) is set. This interrupt can be

disabled through the interrupt enable bit, SPI1IE.

The receive operation is double-buffered. When a

complete byte is received, it is transferred from SPI1SR

to SPI1BUF.

If the receive buffer is full when new data is being

transferred from SPI1SR to SPI1BUF, the module will

set the SPIROV bit indicating an overflow condition.

The transfer of the data from SPI1SR to SPI1BUF is not

completed and the new data is lost. The module will not

respond to SCL transitions while SPIROV is ‘1’, effec-

tively disabling the module until SPI1BUF is read by

user software.

Transmit writes are also double-buffered. The user

writes to SPI1BUF. When the master or slave transfer

is completed, the contents of the shift register

(SPI1SR) are moved to the receive buffer. If any

transmit data has been written to the buffer register, the

contents of the transmit buffer are moved to SPI1SR.

The received data is thus placed in SPI1BUF and the

transmit data in SPI1SR is ready for the next transfer.

Note:

This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals,

descriptions

and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046).

Note:

See

“dsPIC30F

Family

Reference

Manual”

(DS70046)

for

detailed

information on the control and status

registers.

Note:

Both the transmit buffer (SPI1TXB) and

the receive buffer (SPI1RXB) are mapped

to the same register address, SPI1BUF.

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