FT313HQ-R datasheet(17/67 Pages) ETC2

17 / 67 page

Document No.: FT_000589

FT313H USB2.0 HS Host Controller Datasheet Version 1.2

Clearance No.: FTDI# 318

The DMA controller of the FT313H has only one DMA channel. Therefore, only one DMA read or

DMA write may take place at a time. Assign the DMA transfer length in the Data Session

Length register for each DMA transfer. If the transfer length is larger than the burst counter,

the DREQ signal will de-assert at the end of each burst transfer. DREQ will re-assert at the

beginning of the each burst.

When DMA is transferring data from/to local buffer, if it wants to access local buffer content by

PIO mode, can use auxiliary memory access registers AUX_MEMADDR and AUX_DATAPORT to

read/write data from/to local buffer with single cycle.

For a 16-bit DMA transfer, the minimum burst length is 2 bytes. This means that the burst

length is only one DMA cycle. Therefore, DREQ and DACK will assert and de-assert at each

DMA cycle.

The FT313H will be asserted DMA EOT interrupt to indicate that the DMA transfer has either

successfully completed or terminated.

4.7 EHCI host controller

The FT313H is a one-port EHCI-compatible host controller which supports all the USB 2.0

compliant Low-speed, Full-speed, and High-speed devices and split/preamble transactions for

the HS/FS hub.

The EHCI host controller supports two categories of the transfer types, the periodic and

asynchronous transfer types. The periodic transfer type includes the isochronous and interrupt

transfers, while the asynchronous transfer type includes the control and bulk transfers.

The EHCI host controller has schedule interface that provides to the separate schedules for

each category of the transfer type. The periodic schedule is based on a time-oriented frame list

that represents a slide window of time of the host controller work items. All the ISO and INT

transfers are serviced via the periodic schedule. The asynchronous schedule is a simple circular

list of the schedule work items that provides a round robin service opportunity for all the

asynchronous transfers.

The EHCI host controller contains the Isochronous Transfer Descriptor (iTD), Queue Head (qH)

and Queue Element Transfer Descriptor (qTD), and Split Transaction Isochronous Transfer

Descriptor (siTD) data structure interface to support the isochronous/interrupt/control/bulk

transfers and split transaction.

The EHCI host controller internal buffer memory is 24KB. START_ADDR_MEM register is

allocated from 0x0000 to 0x5FFF.

4.8 System clock

4.8.1 Phase Locked Loop (PLL) clock multiplier

The internal PLL supports 12MHz, 19.2MHz, or 24MHz input, which can be crystal or a clock

already existing in system. The frequency selection can be done using the FREQSEL1 and

FREQSEL2 pins. Table 4.3 provides clock frequency selection.

FREQSEL1

FREQSEL2

Clock Frequency

12MHz

19.2MHz

24MHz

Table 4-3 Clock frequency select

FT313HQ-R 数据表(PDF) 17 Page - List of Unclassifed Manufacturers

FT313HQ-R 数据表(HTML) 17 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载