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FT313HQ-R 数据表(PDF) 36 Page - List of Unclassifed Manufacturers |
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FT313HQ-R 数据表(HTML) 36 Page - List of Unclassifed Manufacturers |
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36 / 67 page ![]() Copyright © 2013 Future Technology Devices International Limited 36 Document No.: FT_000589 FT313H USB2.0 HS Host Controller Datasheet Version 1.2 Clearance No.: FTDI# 318 Bit Name Type Default value Description disconnect Indicates that wake up event is triggered. The INT line will be asserted if the respective enable bit in the HCINTEN register is set. 0: No wake up event has occurred on the port when device connects or disconnects. 1: Wake up event has occurred on the port when device connects or disconnects. 6 OCINT R/WC 1’b0 Overcurrent interrupt Indicates that overcurrent event is triggered. The INT line will be asserted if the respective enable bit in the HCINTEN register is set. 0: No overcurrent event has occurred. 1: Overcurrent event has occurred. 5 CLKREADY R/WC 1’b0 Clock ready Indicates that internal clock signals are running stable. The INT line will be asserted if the respective enable bit in the HCINTEN register is set. 0: No clock ready event has occurred. 1: Clock ready event has occurred. 4 BUSINACTIVE R/WC 1’b0 USB Bus inactive interrupt Indicates that USB bus is inactive. The INT line will be asserted if the respective enable bit in the HCINTEN register is set. 0: USB bus is active. 1: USB bus is inactive. 3 REMOTEWKINT R/WC 1’b0 Remote Wake up interrupt Indicates INT was generated when the host controller remote wakeup. The INT line will be asserted if the respective enable bit in the HCINTEN register is set. 0: No remote wake up. 1: Remote wake up event occurred. 2 DMAEOTINT R/WC 1’b0 DMA EOT interrupt Indicates the DMA transfer completion. The INT line will be asserted if the respective enable bit in the HCINTEN register is set. 0: No DMA transfer is completed. 1: DMA transfer is completed. 1 SOFINT R/WC 1’b0 SOF interrupt The INT line will be asserted if the respective bit enable is set. |
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