FT313HQ-R datasheet(24/67 Pages) ETC2

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Document No.: FT_000589

FT313H USB2.0 HS Host Controller Datasheet Version 1.2

Clearance No.: FTDI# 318

Bit

Name

Type

Default value

Description

R/W

1’b0

Run/Stop

When this bit is set to 1b, the host controller

proceeds with the execution of schedule.

0: Stop

1: Run

Table 5-5 USB command register

5.2.5 USBSTS register (address = 14h)

This register indicates pending interrupts and various states of the Host Controller. The status resulting

from a transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this

Bit

Name

Type

Default value

Description

[31:16]

Reserved

16’h0

ASCH_STS

1’b0

Asynchronous Schedule Status

This bit reports the actual status of the

asynchronous schedule.

PSCH_STS

1’b0

Periodic Schedule Status

This bit reports the actual status of the periodic

schedule.

Reclamation

1’b0

Reclamation

This is a read-only status bit, and used to detect

an empty of the asynchronous schedule.

HCHalted

1’b1

Host Controller Halted

This bit is a zero whenever the Run/Stop bit is

set to ‘1.’ The host controller sets this bit to ‘1’

after it has stopped the executing as a result of

the Run/Stop bit being set to 0b.

[11:6]

Reserved

6’b0

INT_OAA

R/WC

1’b0

Interrupt on Asynchronous Advance

This status bit indicates the assertion of interrupt

on Async Advance Doorbell.

H_SYSERR

R/WC

1’b0

Host System Error

The Host Controller sets this bit to ‘1’ when a

serious error occurred during a host system

access involving the host controller module.

FRL_ROL

R/WC

1’b0

Frame List Rollover

The host controller sets this bit to ’1’ when the

Frame List Index rolls over from its maximum

value to zero.

PO_CHG_DET

R/WC

1’b0

Port Change Detect

The host controller sets this bit to ’1’ when any

port has a change bit transition from ‘0’ to ‘1.’

In addition, this bit is loaded with the OR of all of

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