FT313HQ-R datasheet(31/67 Pages) ETC2

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Document No.: FT_000589

FT313H USB2.0 HS Host Controller Datasheet Version 1.2

Clearance No.: FTDI# 318

Bit

Name

Type

Default value

Description

INTR_POL

R/W

1’b0

Interrupt Polarity

0: active LOW

1: active HIGH

INTR_LEVEL

R/W

1’b0

Interrupt Level

0: level trigger

1: Edge trigged. The pulse width

depends on the NO_OF_CLK bits in

the EDGEINTC register.

GLOBAL_INTR_EN

R/W

1’b0

Globe interrupt enable

0: INT assertion disabled. INT will

never be asserted, regardless of

other settings or INT events.

1: INT assertion enabled. INT will be

asserted according to the HCINTEN

occurrence.

Table 5-14 HW mode register

5.3.4 EDGEINTC register (address = 88h)

Bit

Name

Type

Default value

Description

[31:24]

MIN_WIDTH

R/W

8’b0

Minimum Interval

Indicates the minimum interval between two

edge interrupts in uSOFs (1 uSOF = 125us).

This is not valid for level interrupts. A count

of zero means that an interrupt occurs as

when an event occurs.

[23:16]

Reserved

8’b0

[15: 0]

NO_OF_CLK

R/W

16’b1F

Number of clocks

Number of clocks that an Edge Interrupt

must be kept asserted on the interface. The

default INT pulse width is approximately

500ns. (N+1)*60MHz system clock.

Table 5-15 Edge interrupt control register

5.3.5 SWRESET register (address = 8Ch)

Bit

Name

Type

Default value

Description

[15: 8]

Reserved

8’b0

[7: 6]

INTF_MODE

2’b00

Interface mode

00b: Reserved

01b: Generic

Multiplex mode

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