| 数据搜索系统,热门电子元器件搜索 |
|
FT313HQ-R 数据表(PDF) 52 Page - List of Unclassifed Manufacturers |
|
|
|||||||||||||||||||||||||||||
FT313HQ-R 数据表(HTML) 52 Page - List of Unclassifed Manufacturers |
|
52 / 67 page ![]() Copyright © 2013 Future Technology Devices International Limited 52 Document No.: FT_000589 FT313H USB2.0 HS Host Controller Datasheet Version 1.2 Clearance No.: FTDI# 318 6.4.2 DMA timing DMA timing characteristics (Ambient Temperature = -40°C to +85°C) Parameter Description Min Max Unit Tsudreqdack DREQ Set-up Time before DACK Assertion 0 - ns Tddackdreq DACK De-assertion to Next DREQ Assertion Time 18 - ns Thdreqdack DREQ Hold Time after Last Strobe Assertion - 35 ns Trwp RD_N/WR_N Pulse Width 40 - ns Toe Data Valid Time after RD_N Assertion 8 - ns Trdh Read Data Hold Time after RD_N De- asserts 4 9 ns Twdh Write Data Hold Time after WR_N De- assertion 0 - ns Tdadvh Write Data Set-up Time before WR_N De-assertion 6 - ns Tsudackrw DACK Set-up Time before RD_N/WR_N Assertion 0 - ns Trwdack DACK De-assertion after RD_N/WR_N De-assertion 0 - ns Tcyc DMA Read/Write Cycle Time 80 - ns Table 6-13 DMA timing DREQ DACK RD_N/ WR_N DATA[15:0] (read) DATA[15:0] (write) Tsudreqdack Tsudackrw Trwp Tcyc Thdreqdack Tddackdreq Trwdack Toe Trdh Tdadvh Twdh DATA1 DATA2 DATAn Figure 6-7 DMA read and write |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |