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AD9853 数据表(PDF) 6 Page - Analog Devices

部件名 AD9853
功能描述  Programmable Digital QPSK/16-QAM Modulator
PDF  31 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9853 数据表(HTML) 6 Page - Analog Devices

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OBSOLETE
AD9853
–6–
REV. C
Table II. Control Register Functional Assignment
Register
Address
DATA
(Note 1)
D7
D6
D5
D4
D3
D2
D1
D0
00h
MSB
Value of K (Message Length in Bytes) for Reed-Solomon Encoder, where 1610 ≤ K ≤ 25510 (Note 2)
LSB
01h
MSB
The Number of Correctable Byte
LSB
Randomizer
Randomizer Length
(Note 3)
Errors (t) for the Reed-Solomon
Insertion
002 = 6 Bit
Encoder, where 0
≤ t ≤ 10
10.012 = 15 Bit
For t = 0, the RS encoder is
0 = After RS
102 = Randomizer OFF
effectively disabled.
1 = Before RS
112 = Randomizer OFF
02h
MSB
Lower Eight Bits of Seed Value for 15-Bit Randomizer (Not Used for 6-Bit Randomizer)
LSB
03h
MSB
Upper Seven Bits of Seed Value for 15-Bit Randomizer
LSB
– OR –
Seed Value for 6-Bit Randomizer (D1 not used in this case).
04h
MSB
Preamble Length (L) where 0
≤ L ≤ 96 Bits (Note 4)
LSB
05h
Modulation Mode
0002 = QPSK , 0012 = DQPSK, 0102 = 16-QAM
0112 = D16-QAM , 1002 = FSK
06h
The MSB of the preamble always resides in D7 of Address 11h and is the first preamble bit to be clocked out of the device during transmission of
:
a packet. Up to 96 bits of preamble are available as specified in Register 04h. Unused bits are don’t care for L < 96.
11h
MSB
Preamble Data. (Note 5)
12h
MSB
Interpolator #1: RATE
LSB
Rate Change Factor (R) where 310 ≤ R ≤ 3110
13h
MSB
Interpolator #2: RATE
LSB
Rate Change Factor (R) where 210 ≤ R ≤ 6310
14h
MSB
Interpolator #1: SCALE
LSB
2
× Multiplier
0 = OFF
1 = ON
15h
6
MSB
Interpolator #2: SCALE
LSB
16h
Frequency Tuning Word #1
LSB
:
FSK Mode: Specifies the “space” frequency (F0).
19h
MSB
All Other Modes: Specifies the carrier frequency.
1Ah
Frequency Tuning Word #2
LSB
:
FSK Mode: Specifies the “mark” frequency (F1).
1Dh
MSB
(Addresses 1Ah–1Dh are only valid for FSK mode.)
1Eh
5
MSB-2
MSB-3
10-Bit FIR End Tap Coefficient, a0
LSB0
1Fh
MSB0
MSB-1
<— — — — — — — — — — — — — — Unused Bits — — — — — — — — — — — — — —>
:
:
FIR Intermediate Tap Coefficients, a1 – a19
:
46h
MSB-2
MSB-3
10-Bit FIR Center Tap Coefficient, a20
LSB20
47h
MSB20
MSB-1
<— — — — — — — — — — — — — — Unused Bits — — — — — — — — — — — — — —>
Spectrum
Digital Power
6
× RefClk
PLL Mode
DAC Mode
48h
0 = I
× Cos + Q × Sin
0 = Normal
0 = Off
0 = Awake
0 = Awake
(Note 7)
1 = I
× Cos – Q × Sin
1 = Shutdown
1 = On
1 = Sleep
1 = Sleep
49h
AD8320 Cable Driver Gain Control Byte (GCB)
(Note 8)
MSB
The absolute gain, AV, of the AD8320 is given by: AV = 0.316 + 0.077 × GCB (where 0 ≤ GCB ≤ 25510)
LSB
NOTES
1The 8-bit Register Address is preceded by an 8-bit Device Address, which is given by
000001XY, where the value of Bits X and Y are determined as follows:
X
Voltage Applied to Pin 6
Y
Desired Register Function
0
GND
0
WRITE
1+VS
1
READ
2This register must be loaded with a nonzero value even if the RS encoder has been
disabled by setting T = 0 in register 01h.
3Unused regions are don’t care bit locations.
4If a preamble is not used this register must be initialized to a value of 0 by the user.
5Addresses 06h–011h and 1Eh–47h are write only.
6Readback of register 15h results in a value that is 2
× the actual programmed value.
This is a design error in the readback function.
7Assertion of RESET (Pin 32) sets the contents of this register to 0.
8Registers 0h–48h may be written to using a single register address followed by a
contiguous data sequence (see Figure 27). Register 49h, however, must be written to
individually; i.e., a separately addressed 8-bit data sequence.



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