AD9853_15 datasheet(26/31 Pages) AD

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OBSOLETE

AD9853

–26–

REV. C

around the constellation has simply been reversed. This effect

also holds true for the 16-QAM and D16-QAM constellations

shown in the respective I

× COS – Q × SIN and I × COS + Q ×

SIN mappings shown in Figure 37.

DIRECT DIGITAL SYNTHESIZER FUNCTION

The direct digital synthesizer (DDS) block delivers the sine/cosine

carriers that are digitally modulated by the I/Q data paths. The

DDS function is frequency tuned via the control bus with a

32-bit tuning word. This allows the AD9853’s output carrier

frequency to be very precisely tuned while still providing output

frequency agility.

The equation relating output frequency of the AD9853 digital

modulator to the frequency tuning word (FTWORD) and the

reference clock (REFCLK) is given as:

fOUT = (FTWORD

× REFCLK)/232

where: fOUT and REFCLK frequencies are in Hz and FTWORD

is a decimal number from 0 to (2

32)/2

Example: Find the FTWORD for fOUT = 41 MHz and REFCLK

= 122.88 MHz

If fOUT = 41 MHz and REFCLK = 122.88 MHz, then:

FTWORD = 556AAAAA hex

Loading 556AAAAAh into control bus registers 16h–19h programs

the AD9853 for fOUT = 41 MHz, given a REFCLK frequency of

122.88 MHz.

D/A CONVERTER

Up to this point all the processing has been in the digital domain.

In order to pass the modulated signal onto the cable driver for

amplification to the levels required to drive the 75 ohm cable, a

digital-to-analog converter (DAC) is implemented. The DAC

needs to have good enough transient characteristics so as not to

add significant spurious in the spectrum. Typically the worst

spurs from the DAC are due to harmonics of the fundamental

signal and their aliases (please see the AD9850 complete-DDS

data sheet for a detailed explanation of aliased images). These

harmonics are worst case for the higher carrier frequencies. The

AD9853 contains a wideband 10-bit DAC which maintains

spurious-free dynamic range (SFDR) performance of –50 dBc

up to 42 MHz AOUT and –44 dBc up to 65 MHz AOUT.

The conversion process will produce aliased components at the

DAC output at n

× f

CLOCK ± fCARRIER (n = 1, 2, 3, ...). These

are typically filtered with an external RLC filter between the

DAC and the line driver amplifier. Again, it is important for this

analog filter to have a sufficiently flat gain and linear phase

response across the bandwidth of interest so as to avoid the

aforementioned modulation impairments. A relatively inexpen-

sive seventh order elliptical low-pass filter is sufficient to sup-

press the aliased components for HFC network applications.

The AD9853 provides true and complement outputs, Pins 24

and 25, which are current outputs. The full-scale output current

is set by the RSET resistor at Pin 18. The value of RSET for a

particular IOUT is determined using the following equation:

RSET = 32 (1.248 V/IOUT)

For example, if a full-scale output current of 20 mA is desired,

then RSET = 32(1.248/0.02), or approximately 2 kΩ. Every

doubling of the RSET value will halve the output current. Maxi-

mum output current is specified as 20 mA.

The full-scale output current range of the AD9853 is 5 mA–20 mA,

with 10 mA being the optimal value for best spurious-free

dynamic range (SFDR). Full-scale output currents outside of

this range will degrade SFDR performance. SFDR is also slightly

affected by output matching, that is, for best SFDR, the two

outputs should be equally terminated.

The output load should be located as close as possible to the

AD9853 package to minimize stray capacitance and inductance.

The load may be a simple resistor to ground, an op amp cur-

rent-to-voltage converter, or a transformer-coupled circuit. It is

best not to attempt to directly drive highly reactive loads (such

as an LC filter). Driving an LC filter without a transformer

requires that the filter be doubly terminated for best performance,

that is, the filter input and output should both be resistively

terminated with the appropriate values. The parallel combina-

tion of the two terminations will determine the load that the

AD9853 will see for signals within the filter passband. For ex-

ample, a 50

Ω terminated input/output low-pass filter will look

like a 25

Ω load to the AD9853. The resistor at the filter input

will mask the reactive components of the LC filter and provide a

termination for signals outside the filter pass band.

The output compliance voltage of the AD9853 is –0.5 V to

+1.5 V. Any signal developed at the DAC output should not

exceed +1.5 V, otherwise, signal distortion will result. Further-

more, the signal may extend below ground as much as 0.5 V

without damage or signal distortion. The use of a transformer

with a grounded center-tap for common-mode rejection results

in signals at the AD9853 DAC output pins that are symmetrical

about ground.

As previously mentioned, by differentially combining the two

signals the user can provide some degree of common-mode

signal rejection. The amount of rejection is dependent upon

how closely the common-mode signals of each output are

matched in amplitude and phase. If the signals are exactly alike,

then ideally, there would be 100 percent rejection in a perfect

differential amplifier or combiner. A differential combiner might

consist of a transformer or an op amp. The object is to combine

or amplify only the difference between two signals and to reject

any common, usually undesirable, characteristic, such as 60 Hz

hum or “clock feed through” that is present on both input sig-

nals. The AD9853 true and complement outputs can be differ-

entially combined and, in fact, are configured as such on the

AD9853-XXPCB evaluation board. This evaluation board

utilizes a broadband 1:1 transformer with a grounded, center-

tapped primary to perform differential combining of the two

DAC outputs.

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