AD9853_15 datasheet(27/31 Pages) AD

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OBSOLETE

AD9853

–27–

REV. C

REFERENCE CLOCK MULTIPLIER

Due to the fact that the AD9853 is a DDS-based modulator, a

relatively high frequency system clock is required. For DDS

applications the carrier is typically limited to about 40% of

fCLOCK. For a 65 MHz carrier, the system clock required is

above 150 MHz. To avoid the cost associated with these high

frequency references, and the aggravating noise coupling issues

associated with operating a high frequency clock on a PC board,

the AD9853 provides an on-chip 6

× clock multiplier. With the

× on-chip multiplier, the input reference clock required for the

AD9853 can be kept in the 20 MHz to 30 MHz range, which

results in cost and system implementation savings. The 6

REFCLK multiplier maintains clock integrity as evidenced by

the AD9853’s system phase noise characteristics of –100 dBc/Hz

and virtually no clock related spurious in the output spectrum.

External loop filter components consisting of a series resistor

(1.3 k

Ω) and capacitor (0.01 µF) provide the compensation

zero for the 6

× REFCLK PLL loop. The overall loop perfor-

mance has been optimized for these component values.

Table VI. Derivation of Currently Transmitted Symbol

Quadrant

Current

MSBs of

MSBs for

Input

Quadrant

Previously

Currently

Bits

Phase

Transmitted

I Q

Change

Symbol

180

270

Note: This table applies to both DQPSK and D16-QAM formats.

In DQPSK a symbol is comprised of two bits that are denoted

as “ I(1) Q(1).” In this case, I(1) and Q(1) are the MSBs and

the table can be interpreted directly. In D16-QAM a symbol is

defined as comprised of four bits denoted as “I(1) Q(1) I(0) Q(0).”

I(1), Q(1) are the MSBs and I(0), Q(0) are the LSBs. As indi-

cated in the table, only the MSBs I(1) and Q(1) are altered as a

function of the differential coding; I(0) and Q(0) are not altered.

DEVICE THERMAL CONSIDERATIONS

The AD9853 is specified to operate at an ambient temperature

of up to +85

°C. The maximum junction temperature (T

J) is

specified at +150

°C, which provides a worst case junction-to-air

differential of +65

°C. Thus, with the specified θ

JA of +36

°C/W,

a maximum device dissipation of 1.8 W is achievable under the

worst case conditions. It is important to understand that a sig-

nificant portion of the heat generated by the device is trans-

ferred to the environment via the package leads. The specified

JA value assumes that the device is soldered to a multilayer

printed circuit board (PCB) with the device power and ground

pins connected directly to power and ground planes of the PCB.

The amount of power internally generated by the device is pri-

marily dependent on four factors:

•

Power Supply Voltage

•

System Clock Rate

•

Input Data Rate

•TXENABLE Duty Cycle (assuming the device is operated in

the burst data mode)

The power generated by the device increases with an increase in

any one of the four factors. It turns out that the contribution of

generated power due to the system clock rate, input data rate

and TXENABLE duty cycle may be ignored at power supply

voltages of less than 4 V (as the total power generated by the

device will not exceed 1.8 W). However, for supply voltages

greater than 4 V, operation at +85

°C ambient temperature will

require a tradeoff among the other three factors; i.e., a reduced

system clock rate, a reduced data rate, a reduced TXENABLE

duty cycle, or some combination of the three. It should be men-

tioned, that operation at a power supply voltage of 4 V yields the

same level of performance as specified at 5 V operation. For

example, the user may still take advantage of the 165 MHz

maximum system clock rate specified for 5 V operation.

VDD

IOUT

IOUTB

DIGITAL

OUT

VDD

(b)

VDD

DIGITAL

(a)

(c)

Figure 38. Equivalent I/O Circuits

AD9853-xxPCB EVALUATION BOARD

Two versions of evaluation boards are available for the AD9853

digital QPSK/16-QAM modulator: the AD9853-45PCB and

the AD9853-65PCB. The – 45 contains a 45 MHz low-pass

filter to support a 5 MHz–42 MHz output bandwidth and the

–65 has a 65 MHz low-pass filter to support a 5 MHz–65 MHz

output bandwidth.

Both versions of the evaluation board contain the AD9853

device, a REFCLOCK oscillator, a seventh order elliptic low-

pass filter of the designated frequency, an AD8320 program-

mable cable driver amplifier, operating software for Windows

3.1 or Windows 95, and a booklet of complete operating in-

structions and performance graphs. The evaluation board pro-

vides an optimal environment for menu-driven programming of

the devices and analysis of output spectral performance.

Part Number

On-Board Low-Pass Filter

AD9853-45PCB

45 MHz

AD9853-65PCB

65 MHz

Windows is a registered trademark of Microsoft, Corporation.

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