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AD9853 数据表(PDF) 28 Page - Analog Devices |
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AD9853 数据表(HTML) 28 Page - Analog Devices |
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28 / 31 page ![]() OBSOLETE AD9853 –28– REV. C C33 10 F +10V FEC (SW2) FUNCTIONS JUMPER FUNCTION 1-2 SOFT FEC ENABLE/DISABLE 2-3 HARD FEC DISABLE OPEN HARD FEC ENABLE OR EXTERNAL FEC CONTROL VIA J11 WHEN USING TRANSFORMER T1A, REMOVE R3 AND R6 WHEN NOT USING T1A, CONNECT E13 TO E14 AND LEAVE R3 AND R6 IN PLACE TST1 HI 4DM J9 2 4 6 8 10 12 14 1 3 5 7 9 11 13 REST E13 T1A T1 – 1T SIG R6 25 4 2 6 1 : 1 E14 GND AVDD DAC BL AVDD AGND DAC RSET NC AGND PLL FILTER PLL VCC PLL GND GND CA CLK CA DATA DGND DVDD REF CLK IN DGND DVDD DATA IN TX ENABLE DVDD DGND AD9853 U1 34 CAC CAD DUT+V CLK DUT+V SDI TXE DUT+V 44 TST1 SMB J10 EXTERNAL FEC ENABLE R7 3.9k +5V FECC 1 2 3 SW2 H3M DIGITAL MODULATOR 22 12 21 20 19 18 17 16 15 14 13 C31 0.1 F R4 3.9k DUT+V C10 0.01 F 33 23 32 31 30 29 28 27 26 25 24 CAE GND 1 3 DUT+V DUT+V DUT+V GND GND R5 1300 NOTE: C31 NORMALLY NOT POPULATED 35 36 37 38 39 40 41 42 43 1 11 2 345 67 89 10 C25 0.1 F DUT+V C24 0.1 F DUT+V C23 0.1 F DUT+V C30 0.1 F DUT+V C29 0.1 F DUT+V DAC OUT/ FILTER IN SMB J6 E9 E1 E10 SIG E2 SIG R3 50 C6 68pF (33pF) C3 7pF (6.8pF) 1 2 C9 56pF (39pF) E3 E4 E11 E12 AMP SMB J7 FILTER OUT/ AMP IN C7 100pF (82pF) C4 33pF (33pF) C5 22pF (27pF) C8 82pF (82pF) L1 120NH (180NH) L2 100NH (100NH) L3 100NH (150NH) 1 2 12 7TH ORDER ELIPTIC 50 LOW PASS FILTER VALUES IN PARENTHESES – 45 MHz FILTER VALUES NOT IN PARENTHESES – 65 MHz FILTER TXENABLE JUMPER CONFIGURATION JUMPER FUNCTION E5-E6 HEADER CONNECTOR FROM DG2020, DATA GENERATOR E7-E8 SOFTWARE CONTROL OF TXENABLE OPEN HARD ENABLE OR EXT. CONTROL VIA J4 T XENABLE E7 E5 E8 E6 SMB J4 R11 3.9k +5V TXE TXEE GND +5V C17 0.1 F Y1 14 VCC OUT 8 GND SW41 CLK SMB J2 R1 50 EXTERNAL CLK 7 CRYSTAL OSC. IF CLOCK REMOVE SOURCE IS Y1 J2 (EXTERNAL) R1 Y1 (XTAL) JUMPER FUNCTION 1-2 HARD POWER-DOWN 2-3 HARD POWER-DOWN OR EXTERNAL CONTROL VIA J3 NO JUMPER POWERED UP AD8320 POWER-DOWN SW1 FUNCTIONS 8PPT+5V RZ1 2 3 4 5 6 7 8 LATCH BUSCLK BUSDAT RESET TXEN BDAT TSTATE 2.2k PULL-UP NETWORK TO +5V THREE-STATE BUFFER U4 74AC244 2A4 2Y4 2A3 2Y3 2A2 2Y3 2A1 2Y2 1A4 1Y4 1A3 1Y3 1A2 1Y2 1A1 1Y1 17 15 13 11 8 6 4 2 GND GND GND BDAT DAT 3 5 7 9 12 14 16 18 RBAK BDAT 1G 2G TSTAT 19 1 +5V C22 0.1 F LATCH +5V R8 3.9k FEC U3 74ACT573 9 8 7 6 5 4 3 2 TXEN TSTATE RESET BUSDAT BUSCLK 12 13 14 15 16 17 18 19 FECC TXEE TSAT REST DAT BCLK 11 1 LATCH C34 0.001 F 8D 8Q 7D 7Q 6D 6Q 5D 5Q 4D 4Q 3D 3Q 2D 2Q 1D 1Q EN OE +5V C21 0.1 F "CENTRONICS" PRINT PORT CONN. C36CRPX LATCH BUSCLK BUSDAT RESET FEC TXEN TSTATE RBAK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 J1 C20 10 F +10V TB1 POWER INPUT CONNECTOR DUT+V GND +5V GND +10V 1 2 3 4 5 75 OUTPUT SMB 75 J8 C12 0.1 F C2 0.1 F VCCL VIN VREF VCC GND GND BYP GND GND GND 20 19 18 17 16 15 14 13 12 11 +10V +10V CAD CAC CAE GND PDN +10V +10V +10V C32 0.1 F PROGRAMMABLE GAIN AMPLIFIER C1 0.1 F C11 0.1 F R2 62 AMP SDATA CLK DATEN GND VOCM PD VCC VCC VCC VOUT AD8320 U2 1 2 3 4 5 6 7 8 9 10 C16 0.1 F +10V SERIAL DATA IN SMB J5 R12 3.9k +5V SDI SDI SMB J3 PODN R10 3.9k AD8320 EXTERNAL POWERDOWN 1 2 3 GND PDN PODN H3M SW1 AD8320 POWERDOWN SOURCE SWITCH C26 0.1 F DUT+V C27 0.1 F DUT+V C28 0.1 F DUT+V C15 0.1 F +10V C19 10 F DUT+V C13 10 F +10V C14 0.1 F +10V C18 10 F +5V Figure 39. Electrical Schematic of AD9853-xxPCB Evaluation Board |
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