AD9853_15 datasheet(22/31 Pages) AD

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OBSOLETE

AD9853

–22–

REV. C

The goal of interpolation is to up-sample the baseband informa-

tion to the system clock rate and to suppress aliases in the pass-

band. The system clock rate is the sample rate of the sine and

cosine signal carriers generated by the DDS in the quadrature

modulator stage. Alias suppression is accomplished by the CIC

filters as described previously. For timing synchronization, the

overall interpolation rate must be set such that the bit rate of the

baseband signal be an even integer factor of the system clock

rate. The importance of the relationship between the data and

system clock rates can not be overstressed. It is restated here for

clarity:

The SYSTEM CLOCK RATE must be an EVEN INTEGER

MULTIPLE of the DATA BIT RATE.

Following is a design example that demonstrates the principles

outlined above.

System Requirements:

• Baseband Bit Rate

1.024 Mb/s

• Carrier Frequency

49 MHz

• Modulation Scheme

16-QAM

• System Power

3.3 V

It should be noted that with a 3.3 V power supply, the maxi-

mum system clock rate of the AD9853 is 126 MHz. This sets an

upper bound on the system clock.

The first consideration is to make sure that the required carrier

frequency is within the AD9853’s output frequency range. The

carrier frequency should be

≤ 40% of the system clock rate. The

given carrier frequency requirement of 49 MHz means that a

minimum system clock rate of 122.5 MHz is required; a value

within the range of the AD9853’s 126 MHz capability.

We must next ensure that the system clock rate is an even inte-

ger multiple of the input bit rate. Dividing the system clock rate

(122.5 MHz) by the data rate (1.024 Mbps) yields 119.63.

Obviously this is not an integer, so we must select the nearest

even integer value (in this case, 120) as the data rate multiplier.

Thus, a system clock rate of 122.88 MHz is required (120

1.024 Mbps). With 6

× REFCLK engaged, the reference clock

input will be 1/6th of the system clock rate, or 20.48 MHz.

Finally, the two interpolator rates must be determined. Since

the FIR filter and interpolator stages will be operating on 16-QAM

symbols, the data rate must be converted from bits/second to

symbols/second (baud). Each 16-QAM symbol is composed

of four serial data bits. Therefore, the baud rate at the input to

the FIR filter is 1.024 Mbps/4 = 256k baud. The FIR pulse

shaping filters up-sample by a factor of 4. This fixes the FIR

sample clock at 256k baud

× 4, or 1.024 MSPS. With the FIR

sampling at a 1.024 MSPS rate, and a previously determined

system clock rate of 122.88 MHz, the interpolators must up-

sample by a factor of 120 (122.88/1.024 = 120).

Rule of Thumb: divide the interpolating burden as equally as

possible among the two interpolators.

Since the required rate change ratio is 120, select a value of 10

for interpolator #1 and 12 for interpolator #2 (10

× 12 = 120).

This satisfies the requirements for the two programmable inter-

polator stages.

Thus far we have established the rate change ratios for the inter-

polators. However, there is an additional consideration. By

default, the interpolators have an intrinsic gain (or loss) that is

dependent on the selected interpolation rate. Since there is the

potential to have overall CIC gains of greater than unity, care

must be taken to avoid the occurrence of overflow in the

interpolators.

Interpolator Scaling

Proper signal processing in the AD9853 depends on data propa-

gating through the pulse-shaping filter and interpolator stages

with as flat a baseband response as possible. In addition to the

frequency response issue, it is also necessary to ensure that the

numerical data propagating through the interpolators does not

result in an overflow condition.

As mentioned earlier, the interpolators are implemented using a

CIC filter. In the AD9853, the CIC filter is designed using

fixed-point processing and two cascaded CIC filter sections

(Interpolator #1 and Interpolator #2). It is important to under-

stand that in a CIC filter, the integration portion of the circuit

will require the accumulation of values based on the rate change

factor, R. This means that the size of the data word grows in a

manner dependent on the choice of R. In the case of Interpola-

tor #1, the circuit is designed around a maximum R of 32 and

this results in an output register width of 28 bits. The design of

Interpolator #2 requires an output register width of 25 bits.

I & Q

ENCODER

SYMBOL

CLOCK

41 - TAP

FIR

41 - TAP

FIR

MUX

INTER-

POLATOR

SCALER

INTER-

POLATOR

SCALER

SYSTEM

CLOCK

M = 3...31

N = 2...63

SCALER

INTER-

POLATOR

SCALER

INTER-

POLATOR

MUX

DDS

INVERSE

SINC

FILTER

DAC

SIN( C)

COS( C)

Figure 36. Block Diagram of AD9853 Data Path and Clock Stages

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