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PIC16LC620-04/SS 数据表(PDF) 31 Page - Microchip Technology |
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PIC16LC620-04/SS 数据表(HTML) 31 Page - Microchip Technology |
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31 / 108 page  © 1998 Microchip Technology Inc. Preliminary DS30235G-page 31 PIC16C62X 6.0 TIMER0 MODULE The Timer0 module timer/counter has the following features: • 8-bit timer/counter • Readable and writable • 8-bit software programmable prescaler • Internal or external clock select • Interrupt on overflow from FFh to 00h • Edge select for external clock Figure 6-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the TMR0 will increment every instruction cycle (without prescaler). If Timer0 is written, the increment is inhibited for the following two cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to TMR0. Counter mode is selected by setting the T0CS bit. In this mode Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the source edge (T0SE) control bit (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. The prescaler is shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale value of 1:2, 1:4, ..., 1:256 are selectable. Section 6.3 details the operation of the prescaler. 6.1 TIMER0 Interrupt Timer0 interrupt is generated when the TMR0 register timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit. The interrupt can be masked by clearing the T0IE bit (INTCON<5>). The T0IF bit (INTCON<2>) must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The Timer0 interrupt cannot wake the processor from SLEEP since the timer is shut off during SLEEP. See Figure 6-4 for Timer0 interrupt timing. FIGURE 6-1: TIMER0 BLOCK DIAGRAM FIGURE 6-2: TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER Note 1: Bits T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register. 2: The prescaler is shared with Watchdog Timer (Figure 6-6) RA4/T0CKI T0SE 0 1 1 0 pin T0CS FOSC/4 Programmable Prescaler Sync with Internal clocks TMR0 PSout (2 TCY delay) PSout Data bus 8 Set Flag bit T0IF on Overflow PSA PS2:PS0 PC-1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) Instruction Fetch TMR0 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 T0 T0+1 T0+2 NT0 NT0+1 NT0+2 T0 MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Write TMR0 executed Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 + 1 Read TMR0 reads NT0 + 2 Instruction Executed |
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