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PIC16LC620-04/SS 数据表(PDF) 44 Page - Microchip Technology |
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PIC16LC620-04/SS 数据表(HTML) 44 Page - Microchip Technology |
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44 / 108 page  PIC16C62X DS30235G-page 44 Preliminary © 1998 Microchip Technology Inc. EXAMPLE 8-1: VOLTAGE REFERENCE CONFIGURATION 8.2 Voltage Reference Accuracy/Error The full range of VSS to VDD cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 8-2) keep VREF from approaching VSS or VDD. The Voltage Reference is VDD derived and therefore, the VREF output changes with fluctuations in VDD. The tested absolute accuracy of the Voltage Reference can be found in Table 12-3. 8.3 Operation During Sleep When the device wakes up from sleep through an interrupt or a Watchdog Timer time-out, the contents of the VRCON register are not affected. To minimize current consumption in SLEEP mode, the Voltage Reference should be disabled. MOVLW 0x02 ; 4 Inputs Muxed MOVWF CMCON ; to 2 comps. BSF STATUS,RP0 ; go to Bank 1 MOVLW 0x07 ; RA3-RA0 are MOVWF TRISA ; outputs MOVLW 0xA6 ; enable VREF MOVWF VRCON ; low range ; set VR<3:0>=6 BCF STATUS,RP0 ; go to Bank 0 CALL DELAY10 ; 10 µs delay 8.4 Effects of a Reset A device reset disables the Voltage Reference by clear- ing bit VREN (VRCON<7>). This reset also disconnects the reference from the RA2 pin by clearing bit VROE (VRCON<6>) and selects the high voltage range by clearing bit VRR (VRCON<5>). The VREF value select bits, VRCON<3:0>, are also cleared. 8.5 Connection Considerations The Voltage Reference Module operates independently of the comparator module. The output of the reference generator may be connected to the RA2 pin if the TRISA<2> bit is set and the VROE bit, VRCON<6>, is set. Enabling the Voltage Reference output onto the RA2 pin with an input signal present will increase cur- rent consumption. Connecting RA2 as a digital output with VREF enabled will also increase current consump- tion. The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited drive capability, a buffer must be used in conjunction with the Voltage Reference output for external connections to VREF. Figure 8-3 shows an example buffering technique. FIGURE 8-3: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE TABLE 8-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE Note: - = Unimplemented, read as "0" Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value On POR Value On All Other Resets 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111 VREF Output + – • • VREF Module Voltage Reference Output Impedance R (1) RA2 Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>. |
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