PIC16LC620-04SLASHSS datasheet(41/108 Pages) MICROCHIP

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Preliminary

DS30235G-page 41

PIC16C62X

7.6

Comparator Interrupts

The comparator interrupt ﬂag is set whenever there is

a change in the output value of either comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<7:6>, to

determine the actual change that has occurred. The

CMIF bit, PIR1<6>, is the comparator interrupt ﬂag.

The CMIF bit must be reset by clearing ‘0’. Since it is

also possible to write a '1' to this register, a simulated

interrupt may be initiated.

The

CMIE

bit

(PIE1<6>)

and

the

PEIE

bit

(INTCON<6>) must be set to enable the interrupt. In

addition, the GIE bit must also be set. If any of these

bits are clear, the interrupt is not enabled, though the

CMIF bit will still be set if an interrupt condition occurs.

The user, in the interrupt service routine, can clear the

interrupt in the following manner:

Any read or write of CMCON. This will end the

mismatch condition.

Clear ﬂag bit CMIF.

A mismatch condition will continue to set ﬂag bit CMIF.

Reading CMCON will end the mismatch condition, and

allow ﬂag bit CMIF to be cleared.

7.7

Comparator Operation During SLEEP

When a comparator is active and the device is placed

in SLEEP mode, the comparator remains active and

the interrupt is functional if enabled. This interrupt will

Note:

If a change in the CMCON register

(C1OUT or C2OUT) should occur when a

read operation is being executed (start of

the Q2 cycle), then the CMIF (PIR1<6>)

interrupt ﬂag may not get set.

wake up the device from SLEEP mode when enabled.

While the comparator is powered-up, higher sleep

currents than shown in the power down current

speciﬁcation will occur. Each comparator that is

operational will consume additional current as shown in

the comparator speciﬁcations. To minimize power

consumption while in SLEEP mode, turn off the

comparators, CM<2:0> = 111, before entering sleep. If

the device wakes-up from sleep, the contents of the

CMCON register are not affected.

7.8

Effects of a RESET

A device reset forces the CMCON register to its reset

state. This forces the comparator module to be in the

comparator

reset

mode,

CM2:CM0 = 000.

This

ensures that all potential inputs are analog inputs.

Device current is minimized when analog inputs are

present at reset time. The comparators will be

powered-down during the reset interval.

7.9

Analog Input Connection

Considerations

A simpliﬁed circuit for an analog input is shown in

Figure 7-5. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. The analog input therefore, must be between

VSS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latch-up may occur. A

maximum

source

impedance

10 k

Ω

recommended for the analog sources. Any external

component connected to an analog input pin, such as

a capacitor or a Zener diode, should have very little

leakage current.

FIGURE 7-5:

ANALOG INPUT MODEL

RS < 10K

AIN

CPIN

5 pF

VDD

VT = 0.6V

RIC

ILEAKAGE

±500 nA

VSS

Legend

CPIN

= Input Capacitance

= Threshold Voltage

ILEAKAGE

= Leakage Current At The Pin Due To Various Junctions

RIC

= Interconnect Resistance

= Source Impedance

= Analog Voltage

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