SPEAR320S-2 datasheet(78/113 Pages) STMICROELECTRONICS

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Timing requirements

SPEAr320S

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Doc ID 022508 Rev 2

Timing requirements

This chapter provides the timing requirements for the synchronous and asynchronous IPs

present in SPEAr320S.

The signal transition levels used for timing measurements are: 0.2*VDD and 0.8*VDD.

5.1

External interrupt timing characteristics

In legacy modes, all the interrupts are high-level triggered. In extended mode, interrupt

trigger polarity is programmable as rising or falling edge.

5.2

Reset timing characteristics

Note:

Warm reset can be triggered by software by writing any value to the system controller

SYSSTAT register.

Table 49.

PL_GPIO external interrupt input timing

Symbol

Description

Min

Unit

tINT

Minimum width for rising edge interrupt pulse

Table 50.

Reset timing characteristics

Symbol

Description

Min

Unit

tRP(cold)

MRESET pin active low state duration for cold

reset (startup time from all supplies up and

stable).

See Figure 7: Cold reset release on page 77)

2ms

tRP(warm)

MRESET pin active low state duration for warm

reset (minimum pulse width able to reset the

device).

See Figure 8: Warm reset release on page 77)

1µs

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