SPEAR320S-2 datasheet(37/113 Pages) STMICROELECTRONICS

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SPEAr320S

Pin description

Doc ID 022508 Rev 2

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3.4

Shared IO pins (PL_GPIOs)

The 98 PL_GPIO and 4 PL_CLK pins have the following characteristics:

●

Output buffer: TTL 3.3 V capable up to 10 mA

●

Input buffer: TTL, 3.3 V tolerant, selectable internal pull up/pull down (PU/PD)

The PL_GPIOs can be configured in different modes. This allows SPEAr320S to be tailored

for use in various applications like:

●

Metering concentrators

●

Large power supply controllers

●

Small printers

3.4.1

PL_GPIO / PL_CLK pins description

Note:

The I/O direction depends on the currently configured multiplexing option and can be

different from the I/O direction at reset. Refer to Table 15: PL_GPIO/PL_CLK multiplexing

scheme and reset states.

3.4.2

Extended mode: RMII automation networking mode

When Extended mode is selected the I/O functions can be selected individually from the

columns of Table 15 using 11 RAS_iosel_regx registers which provide 3-bit configuration

fields for selecting the I/O functions on each of the 102 GPIO I/O pins. (see Table 15:

PL_GPIO/PL_CLK multiplexing scheme and reset states).

This mode provides a fully flexible way of configuring the I/O functions for different

applications. It is forward compatible with the 4 legacy configuration modes and features

enhanced interrupt management with programmable edge polarity.

For example:

●

3 independent SSP synchronous serial ports (SPI, Microwire or TI protocol)

●

2 RMII interfaces

●

Standard parallel port (SPP device implementation)

●

3 independent I2C interfaces

●

7 UARTs

–

1 with hardware flow control (up to 3 Mbps)

–

1 with hardware flow control (baud rate up to 7 Mbps)

–

5 with software flow control (baud rate up to 7 Mbps)

●

4 PWM outputs

Table 13.

PL_GPIO / PL_CLK pins description

Group

Signal name

Ball

Dir.

Description

Pin type

PL_GPIOs

PL_GPIO_97...

PL_GPIO_0

(See

Table 15)

General purpose IO or

multiplexed pins (see

Table 15)

(See the

introduction of

Section 3.4 here

above)

PL_CLK1...

PL_CLK4

Programmable logic

external clocks

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