SPEAR320S-2 datasheet(90/113 Pages) STMICROELECTRONICS

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Timing requirements

SPEAr320S

90/113

Doc ID 022508 Rev 2

Note:

Values in Table 64 refer to the common internal source clock which has a period of tHCLK = 6

ns.

Table 64.

FSMC timing requirements

Symbol

Min

Max

tCLE

-3.9

2.8

tALE

-4.2

2.6

tWE

(1)

Programmable by the Tset bits in the FSMC registers.

(((Tset+1) * tHCLK ) - 3 ns)

(((Tset+1) * tHCLK) + 3 ns)

tRE

(1)

(((Tset+1) * tHCLK ) - 3 ns)

(((Tset+1) * tHCLK) + 3 ns)

tIO

(2)

Programmable by the Thiz bits in the FSMC registers.

(((Thiz +1) * tHCLK) - 3 ns)

(((Thiz +1) * tHCLK )+ 3 ns)

tREAD

(3)

Programmable by the Twait bits in the FSMC registers.

((Twait+1)* tHCLK

Table 65.

FSMC signals timing requirements

Direction

Signal name

Max

Min

Data path

width

Unit

FSMC_CMD_LE

10.57

3.1

FSMC_ADDR_LE

9.5

2.8

FSMC_WE

8.5

2.9

FSMC_RE

8.4

2.75

FSMC_CS0

9.165836

3.07661

FSMC_CS1

8.473722

2.81431

FSMC_CS2

9.172739

3.02958

FSMC_CS3

9.808426

3.21934

FSMC_D7-FSMC_D0

7.710164

2.298715

8-bit

FSMC_D15-FSMC_D8

9.301547

2.420165

8-bit

FSMC_D15-FSMC_D0

9.301547

2.298715

16-bit

FSMC_RDY/BUSY

6.88

1.7

FSMC_D7-FSMC_D0

8.8809

1.18356

8-bit

FSMC_D15-FSMC_D8

10.875302

1.37802

8-bit

FSMC_D15-FSMC_D0

10.875302

1.18356

16-bit

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