SPEAR320S-2 datasheet(9/113 Pages) STMICROELECTRONICS

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SPEAr320S

Description

Doc ID 022508 Rev 2

9/113

Description

SPEAr320S is a member of the SPEAr family of embedded MPUs and is optimized for

industrial automation and consumer markets. The device is based on the ARM926EJ-S

processor (up to 333 MHz), widely used in applications where the processing performance

is required to be higher than the one achievable with microcontrollers.

SPEAr320S provides an integrated MMU (memory management unit) which enables to

support high-level operating systems (HLOS), such as Linux and Windows Embedded

Compact 7. In addition, a rich set of integrated peripherals (memory interfaces, connectivity,

HMI, cryptography) allows the device to be used in a wide range of embedded applications.

The SPEAr320S architecture is based on multiple functional blocks interacting through a

multilayer interconnection bus matrix. The switch matrix structure allows different subsystem

data flows to be executed in parallel improving the core platform efficiency. High

performance master agents are directly interconnected with the memory controller reducing

the memory access latency. The overall memory bandwidth assigned to each master port

can be programmed and optimized through an internal efficient weighted round-robin

arbitration mechanism.

The SPEAr320S device is fully backward-compatible with the previous SPEAr320 product at

both hardware and software programming levels. The extended functionality is achieved by

enhanced I/O multiplexing, preserving the same pinout and ball map, as well as by a new

software-definable configuration mode.

SPEAR320S-2 数据表(PDF) 9 Page - STMicroelectronics