SPEAR320S-2 datasheet(20/113 Pages) STMICROELECTRONICS

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Device functions

SPEAr320S

20/113

Doc ID 022508 Rev 2

2.13

I2C bus ports (I2C)

The SPEAr320S provides three independent I2C bus ports. Each port can be configured as

I2C bus master or slave.

Main features:

●

Compliant to the I2C bus specification (Philips)

●

Support for the 3 standard speeds:

–

Standard (100 Kbps)

–

Fast (400 kbps)

–

High-speed

●

Support for direct memory access (DMA)

●

Clock synchronization

●

Support for slave operation in multimaster environment

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7-bit or 10-bit addressing

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7-bit or 10-bit combined format transfers

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Slave bulk transfer mode

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Transmit and receive buffers

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Interrupt or polled-mode operation

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Handling of bit and byte waiting at all bus speeds

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Digital filter for the received SDA and SCL lines

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Filtering out of legacy CBUS addresses

2.14

Synchronous serial ports (SSP)

SPEAr320S provides three independent synchronous serial ports. Each port can be

configured as master or slave.

Main features:

●

Support for the following protocols:

–

SPI (Motorola)

–

Microwire (National Semiconductor)

–

SSI (Texas Instruments)

●

Programmable parameters:

–

Clock bit rate and prescale

–

Data frame size (from 4 to 16 bits)

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Separate transmit and receive FIFO queues (8 x 16-bit entries)

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Independent masking of transmit FIFO, receive FIFO, and receive overrun interrupts

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Internal loopback test mode available

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DMA interface

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