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SPEAR320S-2 数据表(PDF) 85 Page - STMicroelectronics |
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SPEAR320S-2 数据表(HTML) 85 Page - STMicroelectronics |
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85 / 113 page ![]() SPEAr320S Timing requirements Doc ID 022508 Rev 2 85/113 5.7 Ethernet MII timing characteristics The timing characterization is performed assuming an output load capacitance of 5 pF on the MII TX clock (MII#_TXCLK) and 10 pF on the other pads. 5.7.1 MII transmit timing characteristics Figure 17. MII TX waveform Note: To calculate the tSETUP value for the PHY, you have to consider the next tCK rising edge, so you have to apply the following formula: tSETUP = tCK - tmax Table 58. EMI signals timing requirements Direction Signal name Max Min Unit EMI_A0-EMI_A23 8.612293 1.93584 ns EMD0-EMID15 9.471291 2.260195 EMI_CE0 8.764648 2.90581 EMI_CE1 7.977348 2.636304 EMI_CE2 9.027624 2.930175 EMI_CE3 9.29631 3.006315 EMI_BYTEN0 9.554388 3.092855 EMI_BYTEN1 9.233592 3.038856 EMI_RE 8.193018 2.680564 EMI_WE 8.172619 2.80189 EMI_D0-EMI_D15 10.8188 1.30245 Table 59. MII TX timing requirements Symbol Description Min Max Unit tCK MII#_TXCLK clock period 40 40 ns tD MII#_TXCLK to MII output data delay 3.34 11.86 tD MII#_TXCLK MII#_TXD0-MII#_TXD3, MII#_TXEN, MII#_TXER tck |
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