L9779WD datasheet(76/170 Pages) STMICROELECTRONICS

76 / 170 page

Functional description

L9779WD

76/170

DocID027452 Rev 5

Channel “off”

Short to Vb:

Not available.

Short to GND and open load:

In open load conditions an internal circuit drives the DRAINx voltage to VOUTOPEN with a

maximum pull-up/down current of IOUT_PU and IOUT_PD.

Diagnosis is done comparing driver output voltage with internal voltage thresholds VHVT

and VLVT: if the voltage is below VLVT a short to GND is detected, if the voltage is above

VLVT and below VHVT an open load is detected and if the voltage is above VHVT no fault is

present.

Diagnosis status is masked for Td_mask time after the off event occurs to allow the output

voltage to reach the proper value.

Short to GND and Open load are filtered with TFILTERdiagoff time.

Diag status is latched and reset every Read Diag operation.

6.13

Configurable power stages (CPS) (OUT21 to 28)

6.13.1

Configurable power stages functionality description

L9779 has 4 low-side N-channel power stages and 4 high-side P-channel power stages

[OUT21 to OUT28] that can be arranged as follows using the CPS_CONF1,2 bit (default H-

bridge):



Eight individual power stages (four low-side and four high-side power stages). Low side

can be connected in parallel (in pair) to obtain a low side driver with about 0.75 Ω Rdson

resistance:

OUT22 with OUT24 and OUT27 with OUT28.

For three reasons outputs are switched in parallel:

to increase current capability (please see electrical characteristic)

to reduce power dissipation (please see electrical characteristic)

to increase clamp energy capability (please see electrical characteristic) The max.

clamping energy is probably less than the sum of the corresponding max.

clamping energies.

Parallel connection of Low-side power stages is possible as the control bit to turn-on

and off the power stages is allocated in the same register. Unlike the H-bridge

configuration, no coherency check is done.

OUT21 and OUT25 are able to remain active also during crank pulse during which the

battery voltage on the VB pin goes below the level VB_LV for a period of time THOLD,

this time lapse calculation is triggered by the falling edge of RST In this situation VDD5

is below undervoltage threshold (VDD_UV) and the micro controller is in reset

condition. During the THOLD time the VDD5 supply and the micro controller have to

recover and take over control of the output. Otherwise the output is switching to OFF

condition after the THOLD time.

The low battery functionality can be enabled/disabled through bit OUT21_EN_LB and

OUT25_EN_LB of CONF_REG7.

For the behavior of OUT21, 25 during cranking refer to behavior of OUT13, 14.

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