L9779WD datasheet(32/170 Pages) STMICROELECTRONICS

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Functional description

L9779WD

32/170

DocID027452 Rev 5

6.4

Smart reset circuit

Figure 13. Smart reset circuit

6.4.1

Smart reset circuit functionality description

The RST pin is an input/output active when low. As output pin the Smart Reset circuit takes

into account several events of the device in order to generate the proper reset signal at RST

pin for the microcontroller and for a portion of the internal logic as well. As input pin RST

when driven low by external source for more than Trst_flt, it is used to reset the same

portion of logic of the device.

The sources of reset are:



VDD5 undervoltage disabled by MSC CONFIG_REG6 bit3 = high, default is low i.e.

enabled



Power down



Power latch, KEY_ON



VB overvoltage



VDDIO undervoltage



WDG_RST, query and answer watchdog reset

Smart reset circuit generates RST signal monitoring the VDD5 according to the graph

shown below: when VDD5 falls below VDD_UV_LOW threshold for a time longer than

TfUV_reset Smart Reset circuit asserts a RST signal (driven low) and the flag CRK_RST is

latched and resets every Read Diag operation. When VDD5 recovers to a voltage greater

than VDD_UV_HIGH RST pin is deasserted after Td_UV_rst. The RST pin is also asserted

at the first power-on phase when the KEY_ON pin goes from low to high, as a consequence

of the VDD5 absence.

Smart reset circuit generates an RST signal at power down independently of filtering time

and VDD5 voltage level. During power latch mode if NL_RST bit is set and KEY_ON signal

goes low to high again (before microcontroller was able to write PWL_EN_N=0), RST_PIN

is asserted for time TNL.

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