L9779WD datasheet(128/170 Pages) STMICROELECTRONICS

128 / 170 page

Functional description

L9779WD

128/170

DocID027452 Rev 5

Figure 77. Communication diagram between µC and L9779WD

Downstream communication

Signals

The enable input is active with inverted polarity - i.e.‚ low level during the active phases of

command or data frames. An active enable signal validates the DI input signal. Outside the

active phase (enable line is at high level) invalid data may occur at DI.

The active phase of a downstream frame starts with the falling edge of the enable signal and

ends with the rising edge of the enable signal. The enable signal changes its state with the

rising edge of the clock CL (because CL has normal polarity).

DI changes its state on rising edge and it is latched by L9779WD on the falling edge of CL.

Downstream frames are synchronous serial frames. They support enable signal and

command/data selection bit as part of the frame. Command/data selection bit allows

distinguishing frames as command and data frames in the receiver circuit.

Command frames and data frames may be sent in any sequence with a passive phase of at

least 2 CL-cycles after each frame.

Command frame

A command frame always starts with a high level bit (command selection bit). The number

of the command bit of the active phase of a command frame NCB is fixed to 14. If the

number of the command bit is not equal to NCB = 14 the frame will be ignored, the

command will not be executed and the error flag (TRANS_L) will be set.

The length of the command frame's passive phase tCPP must be a minimum of 2 * tCL.

Execution of the command is finished not later than 16*tCL after the end of active phase.

L9779WD 数据表(PDF) 128 Page - STMicroelectronics