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L9779WD 数据表(PDF) 133 Page - STMicroelectronics |
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L9779WD 数据表(HTML) 133 Page - STMicroelectronics |
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133 / 170 page ![]() DocID027452 Rev 5 133/170 L9779WD Functional description 169 Figure 83. Cycle time diagram Table 62. Time electrical characteristics Pin Symbol Parameter Test condition Min Typ Max Unit CLP, CLN VCLP, VCLN Input voltage range Not to be tested. It is an application note. 0.8 - 1.6 V VCLdiff Differential input voltage VCLdiff =|VCLP-VCLN| 150 - 450 mV VCLdiff Input voltage offset VCLdiff =0.5*(VCLP+VCLN) 1- 1.4 V Rcl EXTERNAL Resistor between CLP and CLN -100 - Rpu_N Internal pull-up resistor - 100 200 400 k Rpd_P Internal pull-down resistor - 100 200 400 k VCL_high Differential input high detection level VCL_high= VCLP_high - VCLN_high -100 mV |
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