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STM32F479AI 数据表(PDF) 172 Page - STMicroelectronics |
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STM32F479AI 数据表(HTML) 172 Page - STMicroelectronics |
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172 / 208 page  Electrical characteristics STM32F479xx 172/208 DocID028010 Rev 2 Table 98. Synchronous multiplexed PSRAM write timings(1) 1. Based on test during characterization. Symbol Parameter Min Max Unit tw(CLK) FMC_CLK period, VDD range= 2.7 to 3.6 V 2THCLK − 1 - ns td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0…2) - 1.5 td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 0 t(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK−0.5 - td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 0 - td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK−0.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 - |
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