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STM32F479AI 数据表(PDF) 174 Page - STMicroelectronics |
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STM32F479AI 数据表(HTML) 174 Page - STMicroelectronics |
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174 / 208 page  Electrical characteristics STM32F479xx 174/208 DocID028010 Rev 2 Figure 64. Synchronous non-multiplexed PSRAM write timings Table 100. Synchronous non-multiplexed PSRAM write timings(1) 1. Based on test during characterization. Symbol Parameter Min Max Unit t(CLK) FMC_CLK period 2THCLK − 1 - ns td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0…2) - 0.5 t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) 0 - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 0 td(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK−0.5 - td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 2.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 0 - td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK−0.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 - |
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