STM32F479AI datasheet(178/208 Pages) STMICROELECTRONICS

部件名	STM32F479AI

功能描述	8- to 14-bit parallel camera interface up to 54 Mbytes

PDF	208 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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178 / 208 page

Electrical characteristics

STM32F479xx

178/208

DocID028010 Rev 2

In all timing tables, the THCLK is the HCLK clock period.

•

For 2.7 V ≤ VDD ≤ 3.6 V, maximum FMC_SDCLK = 90 MHz, at CL = 30 pF (on

FMC_SDCLK).

•

For 1.71 V≤ VDD <1.9 V, maximum FMC_SDCLK = 75 MHz when CAS Latency = 3 and

60 MHz for CAS latency 1 or 2. CL = 10 pF (on FMC_SDCLK).

Figure 69. SDRAM read access waveforms (CL = 1)

Table 103. SDRAM read timings(1)

1. Guaranteed based on test during characterization.

Symbol

Parameter

Min

Max

Unit

tw(SDCLK)

FMC_SDCLK period

2THCLK − 0.5

2THCLK+0.5

tsu(SDCLKH _Data)

Data input setup time

th(SDCLKH_Data)

Data input hold time

td(SDCLKL_Add)

Address valid time

1.5

td(SDCLKL- SDNE)

Chip select valid time

0.5

th(SDCLKL_SDNE)

Chip select hold time

td(SDCLKL_SDNRAS)

SDNRAS valid time

0.5

th(SDCLKL_SDNRAS)

SDNRAS hold time

td(SDCLKL_SDNCAS)

SDNCAS valid time

0.5

th(SDCLKL_SDNCAS)

SDNCAS hold time

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