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MPC875 数据表(PDF) 27 Page - Freescale Semiconductor, Inc |
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MPC875 数据表(HTML) 27 Page - Freescale Semiconductor, Inc |
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27 / 84 page  MPC875/MPC870 Hardware Specifications, Rev. 3.0 27 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 10 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) Figure 10. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1 Figure 11 through Figure 14 provide the timing for the external bus read controlled by various GPCM factors. Figure 11. External Bus Read Timing (GPCM Controlled—ACS = 00) CLKOUT TA D[0:31] B20 B21 CLKOUT A[0:31] CSx OE WE[0:3] TS D[0:31] B11 B12 B23 B8 B22 B26 B19 B18 B25 B28 |
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